Why aren't you using RISC? A CPU that fully respects your freedoms

Why aren't you using RISC? A CPU that fully respects your freedoms

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blog.invisiblethings.org/papers/2015/x86_harmful.pdf
sifive.com/boards/hifive1
github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs
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Because I'm not autistic like most of Jow Forums

risc isn't a specific cpu

>RISC
>A CPU

But does it respect freedom 0?

I'll happily buy a RISC-V SBC once available at a reasonable price.

Once I can buy an arm laptop and run ubuntu on it I will.

How do I know that I'm not using RISC without some kind of sino-american spyware

RISC GOOD

X86_64 BAD

RISC is not a CPU you retard

keep dreaming

There are proprietary RISC CPUs, like most chink ARM implementations and some MIPS stuff from the likes of Cavium.
I'm not using any of that, though.
RISC-V is a fucking meme, OpenPOWER and OpenSPARC are the only proper options if you want a decent non-botnet CPU.

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CONTRARIAN GOOD

EVIDENCE BAD
blog.invisiblethings.org/papers/2015/x86_harmful.pdf

>harmful
That word and I know I'll read some cat-v luddite.

High five is $60

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Oh, it's this retard again.

already do, i have one in my intel cpu
sadfrog.png

Likely to go over the head of most...

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>OpenPOWER and OpenSPARC
>computers from multi-billion international companies
>not botnet
being this dumb

Where? I can only find the 999 dollar one

>RISC processor
>freedoms
Lmao, you have no idea what you're talking about. Look up ARM Trustzone and the trash in Apple's A and T series chips. A processor that uses a RISC architecture isn't automatically safe and secure. Documentation of features through reverse engineering is the only way to figure out if a specific CPU is safe. Something like ColdFire (reduced m68k) is CISC and still safer than a lot of ARM based designs like I mentioned above. That's because it's old and well documented.

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>certain x86 processors have backdoors
>x86 ISA BAD
Wow, it's not like the same thing can't happen for RISC CPUs

sifive.com/boards/hifive1
First link on Google?

My phone uses an ARM based CPU, so I am.

Well risc v can be audited though. All Intel CPUs have backdoors now with the latest vulnerability

Talking out of your ass? How about some sauce?

Why don't you just design your own CPU using a FPGA?

Am not a freetard.

I am using a RISC CPU, it just happens to have a CISC translation layer.
Also x86 respects my freedoms much more than any other architecture because it have to support a legacy standardized hardware unlike ARM or MIPS that can go wild and create the worst locked down architecture from hell you can think of.
There's a reason you can't install linux as easily on an ARM platform, and when you can, generally you have to have a shitty binary blob with you.

>A CPU that fully respects your freedoms
Because it doesn't respect my time.

>Well risc v can be audited though
RISC-V is an instruction set architecture. Not an actual core design that's ready to be etched into silicon. All of the existing implementations are closed source. It's an open source ISA with a closed source implementation. Do you get that yet, reddit? And even if you did get ahold of schematics they'd be worthless. How do you know there isn't undocumented silicon in your chip? You wouldn't unless you started fabricating your own CPUs. And I know you don't have a billion dollars for lithography equipment, a clean room, hundreds of employees to run the facility, etc.

So shut the hell up and go back.

Because it's slow as shit.

MIPS isn't like ARM. If a MIPS machine is locked down it's going to be done in firmware. In fact, the MIPS ISA is now open source and has all kinds of cool shit like SIMD that RISC-V poo in loo shit doesn't have.

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It did. Nowadays it's pretty hard to find a non-RISC machine.

>In fact, the MIPS ISA is now open source
Not really. People say that despite being "open source" it still has a bunch of legal issues.
>and has all kinds of cool shit like SIMD
It has had these instructions since the late 90s.
>that RISC-V poo in loo shit doesn't have.
RISC-V is basically MIPS instruction set with the redesigned decoder, supporting the variable length instructions.

How much do they cost now?

Plenty of open source implementations here:
github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs

There are more out there.

Can I run all of my software with no qualms? If not, are alternatives for every single one of them? Fuck off until you at least have that parity.