Is PCIe gen 5 a meme? What actual benefits would there be for a consumer? GPUs only need PCIe Gen2, let alone gen 4

you think the industry advance their stuff for consumers?

NVLink used for high end server GPUs from Nvidia has a 300GB/s bandwidth.

So x16 PCIe 5.0 being only 128GB/s bandwidth still can't compete to true high end stuff.

modern gpus's being used as a gaming machine cant saturate pcie 2.0 let alone 3.0
they barely can saturate pcie 3.0 only in compute workloads and that only on amd cards

>Is PCIe gen 5 a meme?
No

>What actual benefits would there be for a consumer?
It's not made for consumers.

>GPUs only need PCIe Gen2, let alone gen 4
Come back when you buy an expansion chassis with 8 Tesla GPUs in it.

But nobody's made an NVLink switch yet, or a point-to-point link that's longer than a couple of centimeters.

The absolute state of Jow Forums

>But nobody's made an NVLink switch yet, or a point-to-point link that's longer than a couple of centimeters.
Which is why PCIe 5.0 is surely still necessary.

user i dont know if you actually know what nvlink is
first of all it doesnt work as a standalone feature
second of all the damn thing cant work with 2 or 3 it only works with 4 and more cards splitting the unified bandwidth in half for each direction thats why you dont see boards with thousands of cards installed like before but only modules with 4 of them at each time

source i work for arista

>Which is why PCIe 5.0 is surely still necessary.
Yes, indeed.

>cant work with 2 or 3 it only works with 4 and more cards
I don't see how that's possible considering IBM specifically says Power9 chips can only have UP to 3 per chip.

UP to 3 means it can also have less than 3, and neither UP to 3 or less than 3, is equal to 4 or more like you're saying.

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>The absolute state of Jow Forums
Go ahead an explain it to me. RAM is for storage, it's by definition more persistent than a bus, so why does a bus actually need more bandwidth than the immediate storage for a device other than headroom. For RAM to cache and cache to registers it makes sense, because it works in the opposite direction, going from more persistent to less persistent but here I dont get it.

The 2080ti can 2x SLI over nvlink. Not sure what you're smoking going on about 3 or more only

Your GPU needs to communicate with your CPU, to do this communication, it needs bandwidth to the CPU, this is done with PCIe lanes.

More bandwidth on the PCIe lanes means more data can be moved between your CPU and GPU.

>Go ahead an explain it to me.
>so why does a bus actually need more bandwidth than the immediate storage
Per fucking SECOND user.
Do you really want to wait for a whole fucking second?

Let's say a decent GPU uses PCIe Gen2, fully saturating the bus. The bandwidth of PCIe Gen5 x2 is the same as Gen4 x4 is Gen3 x8 is Gen2 x16. You can hypothetically run a full graphics card off a single port on a laptop, or have MANY ports on a full-size motherboard

>GPUs only need PCIe Gen2
Not really, even 1.0 is fine

Or x2 or x4.

SLI is not the same as connecting it to the CPU. The GPU isn't going to DMA from system RAM any faster.

I wasn't talking about x1

I understand that, but my point is that there are other benefits to using Gen5 in the standard, you could just reduce the number of lanes.

Oh you *like* ATX form factor?

What if I told you there could be a future where your GPU uses a 4 or 5nm process and comes on an m.2 card?

What's the advantage of an M.2 based GPU compared to a motherboard integrated GPU, or CPU integrated GPU?

The whole point in the normal x16 form factor GPUs is for power delivery and heat dissipation.

Well for one, the ability to upgrade.

>guy talks about nvlink
>ignorant summer nvidiot thinks its a fucking bridge

Not how bifurcation works. It will split it into separate lanes so 16x4.0 lanes becomes 2x 8x4.0 lanes. Which if you put a 3.0 device into will run at 8x3.0 speeds.
To do what you're saying you'd need a plx switch and there's no point in having that not be all 4.0 anyway.
See the new x570 chipset that has 4x uplink lanes but offers 12 lanes out plus other sata and USB so it's working as a switch.

I mean, someone relying on a small GPU of that size probably isn't massively concerned with GPU performance.

The idea of a small GPU like that only really makes sense for use-cases that simply don't need much GPU power.

So you don't need enough GPU power to warrant proper PCIe x16 GPU, but you ALSO need to be able to upgrade that GPU every 2-3 years?

Come on, if an M.2 GPU were to ever exist, it would likely be the only GPU ever used in that system, cause by the time you would NEED a GPU upgrade, you'd need a whole platform upgrade anyway.

What does that have to do with the minimum # of devices it can connect? You said 4

They literally call it sli over NVLink bridge in the Turing whitepaper

NVLink provides up to 200GB/s GPU to GPU bandwidth, which is probably what the SLI bridge is doing in a consumer setup.

It's NOT communicating with the CPU at super high speeds though, it's still limited by your PCIe 3.0 slot.

>They literally call it sli over NVLink bridge in the Turing whitepaper
nvidia says A LOT of things that 99% arent true

just like when they did their ray tracing demo at computex with pico pico and they said turing is faster than a dgx module
they forgot to add that they specifically said to the creator to use a dgx instead of the 1080ti

>You said 4
I'm not the person you are replying to, so no.
SLI by today's date is back to back. There is no NVlink switch implementation, so there will not be any NVlink fabrics in near future.

anandtech.com/show/12581/nvidia-develops-nvlink-switch-nvswitch-18-ports-for-dgx2-more

Okay, I should have clearified. No NVlink switch implementation is being developed for the market. The DGX2 is definitively not consumer-grade hardware, as the pricetag is way way way to high for that.

>some retard on Jow Forums
>official, written nvidia technical marketing language that can get them sued

Not the guy you are responding to, but bridge has multiple meanings here.

>only $399k

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Bullshit, you can easily saturate 16x gen3 with multigpu in DX12 and vulkan.
There is a noticeable difference between two 16x gen3 and two 8x gen3.
And intel still makes fucking cucked processors with 16 pci lanes total.

>he thinks a 200 pin propiertary bus is the same with a 26 pin propiertary cable

you cant you will never will especially in mgpu
hell dual gpu cards from amd cant even saturate the bus doing crunching let alone gaming

Not the guy you are responding to, but it's fairly easy to saturate the PCIe bus. CUDAs own bandwidthTest program literally does this.

In dx12 and vulkan all multigpu communications goes through pci lanes. You don't need all these bridges and nvlink etc shit.
Mainstream games just don't use it yet, so you don't know anything about it.

>a benchmark that pushed the hardware to its limits does this

because this is how real world workloads work

that is the case for amd only nvidia still uses the bridges purely because they want more money

I don't know if you are being deliberately stupid or if you just don't know better, but the """"""benchmark"""""" (which it isn't, it even prints out a warning saying that this is not a benchmark), simply copies memory to and from system RAM, something that is extremely common in many use patterns. Look at heavy machine learning workloads with large datasets for example, these easily saturate a single x16 Gen3 link with a single GPU.

>that is the case for amd only
No. That is false.
SLI doesn't work in DX12 at all, like AT ALL.
The only way you can use multigpu there is to communication through pci.

Stop acting like a retarded fanboy. Nvidia does enough dumb shit, you don't need to lie to make them look bad.

that is not something you can CHANGE it on the api user

it utilises the whole card in a way that you will never be able to because the software sc doesnt LET YOU when you are using both compute and graphics pipeline

DX12 doesn't use the bridges by design and all communication goes through pci lanes, you fucking idiot.
What are you trying to argue here?

>it utilises the whole card in a way that you will never be able to because the software sc doesnt LET YOU when you are using both compute and graphics pipeline
It utilises the card in the exact same way you would in CUDA code, by calling cudaMemcpy(). I can prove it by making a small program right here and now. There are plenty of benchmarks that show that Tensorflow workloads are limited by transfer speed between GPU and system RAM.

gist.github.com/enfiskutensykkel/d8eb36843e294a57a320533a326ea2db

Just ignore the peer-to-peer stuff. This program basically just allocates a buffer on the GPU and then copies from/to RAM using cudaMemcpy().

Pic related, I'm easily saturising the Gen3 PCIe connection here. The GPU is a Quadro P620, so it's not even particularly high-end.

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OH NO NO NO NO

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What's your point?

>being so butthurt about being shown wrong that you resort to doxing and shitposting.
Stay classy, Jow Forums

>long dirty hair
>fat
>barely 18 years old, but already balding
I guess it's something you should expect from a reddirtspacer.

What do you mean? You can easily saturate 16x gen3 pci lanes, he is right. I have never argued against that.
He is just a dumb fuck because he exposed his identity.

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I'm 27 years old in that picture, you need to up your doxing game.

You look 17, in a bad way.

Whatever dude. If you weren't a newfriend, you'd realise that I've posted my github intentionally on Jow Forums many times before so I fail to see your point here.

>so I fail to see your point here.
Because, like i already said, you are a dumb fuck.

Yeah, you totally come off as butthurt lol.

How is me being a "dumb fuck" that relevant to the discussion any way, user?

PCIE 5 isn't for consumers, and it's not being marketed that way either. It's for high-end servers.

I could see it being handy for compute workloads and maybe storage but your average user isn't gonna see any effect for a couple decades.

it's mostly just a regular incremental update for potential future changes. maybe in a couple years someone will figure out something that will saturate it.

I actually think that Gen5 is a bit too late. The PCIe roadmap has been anything but fast, and the reason why Nvidia developed NVlink and NVlink2 (which is basically just PCIe on speed) was because PCIe simply wasn't there yet with Gen3. IMO, going through Gen4 is a mistake, but I guess they wanted to push out a couple of things before delaying any further.

This is great for infiniband systems.

I'm he guy you replied to. The short answer is you're an idiot, the long answer is the BANDWIDTH of your card isn't 8GB a sec, it's closer to 800GB/s. My 1080ti has 484GB/s memory bandwidth yet its connection to the cpu at 16x pcie3 is only 15GB/s. Now go thunderbolt 3 and you cripple that by 4 but gain portability and modularity. Hence the importance of pcie4 and 5

>MUH BANDWIDTH IS 800GB/s
>btw it's actually 484GB/s
Good job

Quality post.

>reading comprehension

Wow way to miss the point user, are you actually retarded or just pretending?

He's just butthurt.

what happened here?

enjoy 1fps

Some faggot got shown wrong and sperged out by shitposting.

Anally annihilated

Bump

Most of the bandwidth used by the VRAM is used for internal reads, unless you think the GPU is trying to exchange 800GB/s with the system memory. Games arent HPC like the two above were talking about, you don't have terabytes of data and tons of bidirectional IO. Most games will allocate more memory than they need and then park it pretty much the entire time. The worst offenders would probably be ones that use a lot of gpgpu like for physics or geometry culling

m.youtube.com/watch?v=Mu2G9MaXe3c

Thunderbolt has entirely different set of issues

For games, the capacity for sure isn't extremely important. Latency probably is though, but that's a different story.

I just want to add that it's not the case that only HPC applications are able to saturise the PCIe link, it is one of several bottlenecks for machine learning/tensorflow stuff for example. For most CUDA applications, you should try to interleave memory transfers with kernel launches so you don't end up waiting for transfers to complete.

> What actual benefits would there be for a consumer?
PCIEx1 10GBe cards. I'd argue cheap 10GBe chipsets will flood the market after PCIE5 becomes mainstream.
Also, considering the bandwidth doubles with each generation, one lane of PCIE5 is 16 lanes of PCIE 1, which means external interfaces with one or two lanes of PCIE5 could be widely used for everything. Prepare for eGPU becoming mainstream.

I understand this, I do really. Very fast interconnects are usually used to join up cpus in server motherboards using brand names like intels QPI quick path interconnect or like nvidia custom sli connectors down through the years.

However pcie bandwidth has stalled for years and external devices are gimped by thunderbolt. Plus Intel has been exceptionally stingy with pcie lanes which is why amd are really kicking ass with those of us who want proper fast networking with nvme SAN for our regular work desktops and home servers.

Bottom line external GPU would instantly benefit from pcie 4 and 5 /next gen thunderbolt

they need more bandwidth that GPU?