/rv/ - RISC-V General

ACT I: Old computers was programmed in assembly and it was painfull; the "remedy" was a fuckload of instructions that does things for you.

CISC processors themselves nowadays are just RISC processors with circuitry to divide complex instructions into sequences of smaller, simpler instructions... It's technically supposed to make it easier for the programmer to write programs, but this logic only really applies to asm code.

I think you've misunderstood "reminder" as "baseless claim". Show me what you got.

hackaday.com/2018/02/09/a-risc-v-that-the-rest-of-us-can-understand/ have you guys seen this? pretty neat project

Microcode

ACT II: A side project at intel spent three weeks on an ISA; they accidentially x86.

>It's technically supposed to make it easier for the programmer to write programs
Remember CISC wasn't made this or that way. It's just how CPUs turned out, before RISC happened.
As to whether this applies, I personally do not know anybody who prefers writing or reading CISC asm over RISC asm.
The 68000 family seems to be an exception, but then again it is fairly clean for a non-RISC architecture.

The father of RISC births a minimalistic processor, CISC proves to be wastefull, x86 turns RISC under the hood and VLIW dies epically.

Excellent summary.

ACT IV: Dennard dies, Amdahl dies, Moore dies. VLIW lives on in DSP, TPUs accellerate deep neural networks and RISC-V cleans up the clutter in SoC.

>VLIW
Still used in DSPs and older graphics chips like the mali-400/450

actually dr. david patterson is full of shit because modern compilers can optimize for instruction pipelines that x86 has which makes it much faster than RISC architectures

please don't claim your ISA is better because of some moral aspect (opensource). it isnt better and until a major manufacturer starts building fabs to make RISC chips nobody fucking cares.

How to sound clueless
>and until a major manufacturer starts building fabs to make RISC chips nobody fucking cares.
The chips are literally being made like pancakes, and have been for quite some time.
And... who the fuck builds their own fabs nowadays?

not on the scale that matters
and on top of that, i dont give a shit anyway until a desktop RISC chip is as performant as sandy bridge

You mean like the IBM POWER9?

inb4 "b-but thats not a "desktop chip" REEE"

I wonder how many faggots who mewl about ISAs in 2018 have actually touched an assembler.

No, user, that isn't just faster than Sandybridge, it's faster than any CPU Intel has ever made.
Too bad they cost an arm and a leg. (pun intended)

friendly reminder that Oracle's latest SPARC servers are clocked at 5.0 GHz

Lol the amount of money, research and resources being thrown at RISC-V is impressive, nvidia are using it = game over. It HAS been adopted by the industry, past tense. Just because you're not seeing consumer products yet doesn't mean diddly shit

I wont TOUCH an assember until someone gives me RISC-V! I'm kidding, I've written in x86 and read arm assembly when debugging on an MCU.

You'd be retarded to buy into SPARC now, it's purpose is to hold companies with legacy codebases on SPARC at the threshold of pain forever

It technically isn't, though. IBM hasn't built a POWER/PowerPC workstation in over a decade and probably never will again, modern POWER chips are very much server-focused and so is AIX.
But the shithead you're arguing with shot himself in the foot by not distinguishing RISC-V from RISC designs in general, so I won't defend him.
>jerking off to clock frequency
What year is it? Also SPARC is literally dead, Oracle shitcanned it because nobody was buying it. This is the last run.
This reads like you're laboring under the delusion that because RISC-V has found yet another use in embedded applications that it's soon going to make the jump to the desktop.

>Gigahertzs
Who cares.

>Dr. David Patterson
Happy Turing aware

meant risc-v, the topic of this thread

even the tools who came into this thread to circlejerk about how cool they are for knowing what RISC is don't think RISC-V stands a chance at doing what the shills think it will

>It technically isn't, though
OwO what's this?
raptorcs.com/content/TL2DS1/intro.html

Attached: boardsmall.png (750x500, 198K)

>motherboard with dual 4-core CPUs
>2,925 usd
>motherboard alone
>2,325 usd
>one 18 core power9 cpu
>1335 usd

Attached: 1516332305013.png (656x555, 178K)

thats a cute froggy! ^.^

thank you

Attached: 51c.png (658x545, 176K)

phoronix.com/scan.php?page=news_item&px=Raptor-TALOS2-Initial-Tests

Nuke micro ARM cores

>OwO what's this?
An entry-level server in a pedestal case with PCIe x16 slots that can't run AIX, not at all sanctioned by IBM or cared for by the engineers who decide the direction of future POWER chips, 99% of which will go to datacenters, not offices.

Running a 22-core Xeon in your gaming PC doesn't make it a prosumer chip.

I want benchmarks with the better thunder x2 cpus

Attached: Cavium-ThunderX-2-in-Microsoft-OCP-Project-Olympus-Server.jpg (2416x1265, 518K)

That's cheap, considering it's the fastest available.

How will cisclets ever recover?

The fastest are supposed to be the 24-core, definitely not the pathetic quads you get in the entry level that probably have even shittier single-thread performance too.

A keypoint to power is how its single thread performance actually isn't pathetic.

I can't actually find any decent POWER9 benchmark results to draw a conclusion from, anyway. I'm curious about integer performance, as well. POWER has always been pretty mediocre in integer.

>>It seems that compilers just do better with simple, RISC-like architectures.

I see RISC-V is going the way of Itanium.

You forgot
>not

The pitch for Itanium was after all
>it's too hard to write assembly for but the compilers will figure it out

And RISC-V, like most RISC, does not suffer from this issue.

How can I contribute in a semi-casual way? I could put in a medium amount of hobbyist effort if I knew where to start. I Know VHDL, C, some IC layout and some electronics.

Do you fab?

The pitch for Itanic was
>let's make a static in-order meme and let the compilers do the thing
Fucking nothing stops you from making an OoO RISC-V design (Esperanto are even doing one IIRC).

So what's the pitch for Risc-V?

I don't know what you mean, so no.

An open ISA extendable by just about anyone (yes, even you niggerwhore mommy can potentially design and build a chip based on custom RISC-V implementation).

If you don't fab then I don't think you can help Risc-V at this point.

If it were better enough to warrant right now, the market would adopt it.

Market is adopting it.
It's currently eating ARM from the bottom.

And the first RV64G development kits with an actual ASIC are being sold (expensive AF).
Since google is in, it's not unreasonable to expect SoCs targetting android, perhaps by google itself.

Just like ARM ate x86, MIPS and PowerPC from the bottom... but it never made it further.

No, don't expect phone SoCs any time soon.
The beauty of ARM is the reference cores.
RISC-V works for embedded and such because developing cores that small is cheap.
Even a reference big ARM core is waaay on the expensive side.

ARM is used in high power, high scaled solutions? I'm just unaware, where is this being used?

Only MIPS (and arguably PPC) lived at the bottom.
Besides, the ARM was eating there during phone boom so it's not like anyone cares about getting up there.

Centriq.
Big Apple, Samsung (M3) cores are sizeable enough to rival x86 in per-core
throughput.

So how long before RISC becomes dominant in server/Enterprise?

Never.
x86 is eternal, and with AMD being back with incredibly comptetive datacenter solutions anything ARM has Z E R O chances of being relevant in datacenter, ever.

So RISC has different use cases than CISC? woah

The differences between "RISC" and "CISC" died with P6.

Fabricate, it's shortened to fab... It's the actual process of making the silicon chips

What's stopping him from going to merchant fab and taping out his design?
Assuming he has money for it.

>What's stopping him from going to merchant fab and taping out his design?

You answer your own question man. Nothing is stopping him

>Assuming he has money for it.

I know that fab is short for fabricate, but isn't that just manufacturing plants in asia (except for military/science grade production)? Are there any open source IP core implementations that need contributers?

Heres a brainlet question. Besides having a different way of saying eg. jmp +7, what truely differentiates one instruction set like x86 from another?
Afaik ARM is said to be more power efficient. How can that be?

ARM is not more power efficient, it all depends on implementation (aka design complexity).

Allthough arm is very much used in low power embedded and mobile.

Because ARM provides simple cores for SoCs/microcontrollers.

>Afaik ARM is said to be more power efficient.
Compared to what?