Given the fact physics will be in the way of making smaller transistors...

ok but that would be dumb because you need to maximize surface area for heat dissipation and there is no need for volume so the ideal shape is... a fucking flat chip

That would make the design of the computers quite challenging, unless you make some sort of side pane CPU that have this huge fan on the side.
And no one but asrock would try to do a miniITX board for this.

That would probably be a nightmare in terms of yield

Enjoy your futuristic CPUs costing thousands or tens of thousands of dollars a piece

>physics will be in the way
Why do the physics people have to get in the way of science?

Physics has laws, and the physics people are their lawyers.

We are reaching maximum density on our flat transistors brah

You could do what he suggested.
Think AMD Epyc, but with a much, much larger substrate with a fuckton of interconnected small chips.

Whos the jury then

yea, but what? Are we going to start doubling the size of our chips every year? thats ridiculous. We want to push for more density. If we double the size every year within a decade our computers will be the size of a room.

I would say physics, but then who's the judge?
The problem is that we're reaching a point where you just can't make it more dense.
Electrons simply start teleporting around like a fucking dragon ball Z fight at those scales, and nothing works.
We actually use those teleportings to make flash memory.

You mean like they used to be?

I think they mean interconnected tons of little dies, much better yields!

stacked dies sunk into a multilayer pcb package perhaps, contacts at the bottom and once every few layers
only gotta figure out a way of making the individual dies thin enough and put contacts on both sides... somehow gotta layer the copper traces they put on the actual silicon on both sides instead of only the bottom

I know I've been posting in here about this. Electrons don't teleport around. The size of the gate becomes smaller than an electron wavelength at 7nm. The electron wavelength is a probability distribution of where the electron may be at any point in time. Therefore there is a strong probability that the electron will be on either side of the gate.

I'm agreeing that we need to start building up. We need to work on developing in 3d in my opinion.

Actual solid 3D would be the best idea in terms of bandwith and stuff.
But need to see if it do compensate versus just piling up a bunch of dies.
Also its quite obvious we will need some sort of hole technology to pump liquid thru the die layers to keep everything cool.

so U can afford buying it ?

Interesting stuff man. Hardware isn't my speciality but I'm taking a class covering a lot of whats holding us back from making smaller transistors and finding it interesting.

Another way we can go is to make more complex than transistor components.
That's what the "10nm" fuss is all about.
Trigates etc..

Electrical engineer here, you're wrong. You cannot make the die taller/thicker, it will affect heat dissipation. Furthermore, there is still room the improve the size of each transistor. We are very close to the limit where transistors can no longer be miniaturized due to quantum tunneling (another 10, 20 years at most) , but the technology used as well as the materials and fabrication process can still be improved. If you can no longer make transistors smaller, you can sure as hell make them faster. An example would be to replace silicon with gallium arsenic.

On top of speed and size, there is still power efficiency which can be increased. We still have quite a lot of room to improve, and god knows what tech and scientific advances comes in the future to allows us to make things even more powerful faster and energy efficient.

parallel/distributed computing is the only way to keep scaling indefinitely.

answer is faster communication lines so that we can put multiple CPUs side by side

This desu. Make them as efficient and small as possible and just tie them all together.

can you explain a pi-johnson junction to me?

but i like food :(

Every die is technically already a cube, they're just short cubes. What you're talking about is increasing Z height. Foundries have focused on decreasing height in order to make slimmer packages for thin laptops and phones, but we certainly could make them taller as we start exploring stacked logic or vertical GAAs.

>arsenic

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>there is still power efficiency which can be increased

Another EE here, I was under the impression that power efficiency pretty much only improves with die shrinks?

Different user
Power efficiency largely comes from smaller transistors needing less switching current, better isolation, less leakage. A shorter channel is easier to pass current though, and at a lower level, its also easier to halt, generally speaking. So long as the device has sufficient electrical control for the given channel length this holds true. Short channel effect is a bitch and its the reason why FinFETs and other topologies exist.
Smaller foundry nodes can shrink the size of transistors, but its not always the case that tertiary characteristics improve. In the past some smaller nodes have brought increased leakage and worse power and ISO frequency.

Don't lick your CPU.