Amd zen 5

I was reading some article about the amd roadmap and it said amd zen 5 will be 3nm....
>3nm
Some studies put the beginning of the
quantum domain in 3 to 1nm and others to 5nm so how could this be possible without near 0k temp?

Attached: amd_glow_wallpaper_by_tman5293-d4szjam.jpg (1920x1080, 181K)

Because Samsung marketing magic. Protip, you shouldn't trust their marketing

>mfw im not crazy
thx user

>muh quantum
Just stop.
There are always electrical hurdles to be overcome at any process node. Wires in the die carry current to power transistors right next to signal IO. The short channel effect has always existed. Wire capacitance and parasitic capacitance has always been something to be worked around.
Different materials are utilized where needed, different gate structures are utilized as needed. We stopped using planar gates when they became too leaky. We'll stop using FinFETs when they fail to effectively control these future shorter channels as well. BEOL design considerations will always ensure FEOL structures function without aberrant behavior.

Muh quantum is a populist level meme for redditors, not anyone actually working in a foundry, or anyone working behind the scenes like Applied Materials.

It's marketingspeak. 3 nm does not mean the transistors will be that size which is when the problems you're alluding to would begin to occur.

So there is no way there will be some aberrant behavior on >5nm chips?
Just asking bc i heard that qtf had great precision for em calc...
am i wrong user?

Yeah so another compound or material to speed our micro-processors?

Speak in real terms. What you're talking about is an electron going where you don't want it. Fact of life is electrons will always have some non linear mobility through any material, it only becomes a problem when it interferes with functionality. A perfectly electrically insulated material may still have one or two electrons flying out of it at will, you can't ever keep them 100% in a wire of any size.
When populist level smucks write articles about the presumptive fears of quantum tunneling they're primarily talking about the short channel effect. Thats something we've dealt with forever, there is nothing new about it. On the back end electrons can fly all the fuck over so long as signal integrity is there and all the FEOL structures function reliably. Of course there is more that goes into it. Processes are designed with a BEOL stack, specific materials, specific isotopes of a given material, just to fine tune the electrical properties of every single metal layer to ensure everything works.

Its not like anyone is spending billions of dollars on R&D then saying "Whoops muh Quantum tunneling got us lol" it doesn't work that way.

thx user

So I've been waiting a long time for Zen 2 to release. Should I just wait for Zen 5???

memes aside when will zen 2 release
I want to know whether or not I should wait for it

Picometer or go home.

OP here im waiting for zen 2 and zen 3 will be on am4 so you could use a zen 1 mb with zen 5 so i guess, as always it depends on your current setup and your needs...

EPYC 2 is already in production, its going to sample to some companies like HP and Dell later this year. Rumor is some samples have already gone out.
The 7nm Zen 2 consumer Ryzen CUs will likely follow in the first half of 2019.

sry meant zen 5 will be on am4 but zen 3 will also be on am4

So zen 2 is gonna be faster per ghz than zen?

if based AMD is still based then yeah, expect 3nm in some years (intlel shills at 14++++++++++)

AMD has said that AM4 will be supported until DDR5 comes out, which is supposed to be some time in 2020. I doubt zen 4/5 will be out before then.

yes and less power consuption/heat

some say zen 4 will not happen or will be a zen3+, zen5 will be out in 2022 i think
and probably more ipc

but it is the Samsung 14nm that saved AMD

"""3nm"""

We still don't even have true """7nm""" let alone """10nm""" outside of cell phones.

based waitfag.

The distance is a measure of how wide the node is. The reality is that the actual transistors are just getting taller, defeating the point. The 3 dimensional area is about the same.

>so how could this be possible without near 0k temp?
Simple. Those are marketing names. "3nm" can easily be roughly same size as "7nm".

>but it is the Samsung 14nm that saved AMD
samsung had the know how about low power asic libraries and 14nm.
gf had the know how about big dies, high performance/power consumption dies and the high performance asic libraries.
on gave to the other a part of its expertise.
>Because Samsung marketing magic
do you remember when samsung 28nm was on par with intel 22nm? don't believe intel marketing.
7nm, 5nm, 3nm are going to be manufactured on EUV.
10-7nm is a piece of cake for EUV lithography, whilst 10nm-7nm is the upper limit for immersion/multiple patterning.
More or less the same equipment is used on EUV and BEUV so you'll see advancements from 7nm in a very short time.