INTLEL BTFO

4999$ for GOAT processor
5999$ if they really want those ruppies

64 cores utterly rapes intels 28c $10k part. even if they do end up gluing together 2 of those for 56 cores the price would go way over $10k. I don't see 64c rome below $10k.

They might get away with stuffing eight of these sized cores into one package - heck it physically should fit at a glance, and any connection problems would have similarity with the HBM travails.

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reminds me of bulldozer, and vega, and well, pretty much every time AMD has let me down...

8 dies on one package is a fucking ungodly amount of wiring, it'd probably be the most complex package ever made.

Reminds me of Ryzen`s succes

>Ryzen
>success

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>6 processors that are above the score of that one ryzen processor
0/10 shitpost

you really need to kys

My 2700X makes 1800 HAHA loser

One of which is 5 years old.

have you ever done a cinebench test? it always spews out random processors like that

> caps
Also take note the result is loaded from a file (brown highlight) and therefore could've been modified.

i like shouting when jews suffer

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Heres the layout for EPYC. Two of the cores are relegated, more internal interconnects, while two others have a relatively high number of perimeter connections. Also the left and right perimeters seem underused as opposed to top and bottom. Seems quite a potential for 90 degree reorientation + a second step of relegation (6 relegated, 2 external or maybe 4, 4) with use of more of the now-unconnected pins and interposers.

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Intel can't reliably pump out those 28cores as well as AMD can pump out 64core parts due to the way Infinity Fabric works. The monolithic approach that Intel uses is absolutely done for, especially when it comes to server CPUs, it's extremely hard to scale the number of cores past what Intel is already doing with a monolithic architecture.
AMD will keep destroying Intel the longer they cling onto it. From 64cores to 128cores next year as they get better 7nm yields and costs on the manufacturing go down, while their Zen microarch keeps getting improved.

Surely Intel is going to do something about it at this point. I mean, it's all fine and dandy when AMD is finally competing but Intel still has the mindshare, 28c to 32c isn't that huge of a difference. But now it's going to be a colossal difference, 28c competing against a 64c, it's never going to win in any kind of server workload. It will be even worse when AMD takes the next step.
I'm really glad AMD didn't rest on their laurels from the early Zen results. Push the pedal to the metal and give us 128c CPUs, obliterate Intel where it really hurts. Make this market truly competitive and innovative again.

The spacer in the middle isn't necessary

>muh single core performance!
Now go compare that multicore performance to a 64core Epyc part. It'll get dwarfed 1:10.

It currently uses 2 dies of A and 2 dies of B. How would it work with 8? 4 of type A and type B?

In that pic, you can see processor 1 and processor 4 is the same chip layout. Processor 2 and 3 are the same too.

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...

valid.x86.fr/0xw6rw

I suspect is 6 internal 2 through the pinout ringbus-like. Found another picture that kind of hints at this

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Can you make it look like a octogon?

>64 cores is faster than 12

>niggahurtz
zen 2 and 7nm FinFET say hello

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The test should stop at the 7600K ( 8600K and 7640X have higher cache clock ).

Jesus, imagine the size of that fucking monster.

If the size of 7nm dies are small enough, could they just make only one type of Ryzen chip and connect it in that shape? Should be the same angle at every chip.

Oh and can the AMD chip get the distance shorter ? HBM/HBM2 etc is usually attached with 1mm or less distance between the CPU/GPU.

7nm Zen2 dies would have to be around half the area they are now. The complexity of the package is still beyond absurd.

Current theories for 8+1 die Rome

1. compute dies don't have memory controllers or lanes, just cores and cache, 8 channel and 128 pcie4 on the I/O die
2. compute dies have lanes but not memory controllers, which are on the I/O die
3. compute dies have 1 memory channel per die, I/O die just has pcie4
4. 4 out of 8 compute dies have 2 memory controllers, this one sounds ridiculous but it's possible if AMD is drunk enough or has significantly improved die to die latency.
5. Variation of #3 but has two channels (one is fused off) so the die can be reused for desktop.

I'm going with #1

Or Zen2 is still a moderately sized die, maybe 150mm2, and is 4CCX. The 64c/128t EPYC2 package is still just 4 dies.
Mainstream Ryzen goes to 16c/32 thread while maintaining Dual channel using the same scheme as Threadripper halving its memory compared to EPYC.

Holy fuck
AMD is analraping for real

>quad core
>worse yields
Tell that to Intel's almost 700mm2 monolithic retardation lmao

my 2700x at stock beats the 8700k at housefireGhz. didn't even have to delid. amazing.

>all these speculation
Just wait for the financial report to told the truth

kaby-lake-x was also discontinued lmao

half-assed attempt at trying to get it to fit. The amount of unused die perimeter is interesting.

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>just fuck my latency up senpai

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7nm dies will be half the size of the current ones.

With the layout of EPYC each core in a given CCX has roughly the same average latency when communicating with any core in any other CCX. It may be 130-140ns, but its predictable.
Having random wire lengths and different latency from one CCX to another isn't going to happen. A package that ridiculous isn't happening.

That isn't certain. Transistor count will be higher, they could, and likely will, have more CCXs per die.

I find it funny that AMD becomes successful the moment it sells out to the chinese government. You all hate intel because of the kikes, but AMD is now a chinese government company. Enjoy your backdoored hardware.

>making a semi-custom SoC is "selling out"
lol tech illiterate retard. By your logic AMD sold out to Sony and Microsoft too.
Fucking pathetic, kid.

No. They won't.

Sure.
They're totally going to have 8 dies on a package. With separated memory controllers. And its totally going to have equal wire length to each CCX on each die.
Totally. Thats the route they're going.

Just your average retarded fanboy who doesn't know jack shit about semi-custom SoC business

Are you saying we could get 6 packages in there

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Random whitepaper schematics of whats possible with a given spec doesn't mean it materializes in an product.
Cost and complexity decreasing yields is what matters for margins.

This is literally one of the least complex designs AMD could take, tiny 7nm dies which make phone SoC's look big with practically no uncore and a 14/16nm management die that's practically entirely SerDes, can't get any cheaper.

>making the package more complex
>controlling signalling externally
>exponentially increasing failure points
>hurr this is simple!

>kill off monolithic
>"let's use a philips head for a flat screw!!!"

tsmc.com/english/dedicatedFoundry/technology/7nm.htm
>TSMC set another industry record by launching two separate 7nm FinFET tracks: one optimized for mobile applications, the other for high performance computing applications.
BASED

>64 cores

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How will AMD ever recover when Intel comes out with Copper lake, 2x28C dies

>Implying Intel's die yields are good enough to make two functioning 28c dies

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Probably by not needing immersion cooling, a new platform and not requiring 500W to compete with their 200W at half the cost.
And with that Intel's biggest advantage , their latency is now gone too.

>pooper lake

I missed the amd train- always thought i was too late to the party. should i jump on now and buy some stock?

how will your server room recover when it burned down with Intel's 600W heat

Probably in the bunkers with what is left of humanity when they set the planet on fire.

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GLUED-TOGETHER BINGBUS PFHAAAAHAHH

Why IPC? Performance per Watt is what's important.

>datacenterfire
No, thanks.

>electricity
pic related is assuming you always run your shit at full load 24/7 which is highly unrealistic because your shit would probably snap from all the work. Whatever marginal difference there is in performance per watt in consumer PC hardware is literally irrelevant, Might as well clock your shit down to 1ghz, the performance per watt will be massive

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>512MB L4 cache
but why

I hear Rome has 256MB of L3, the L4 should be much bigger then.

THIS IS NOT ALLOWED, MODS TAKE IT DOWN

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NOOOOOO

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8x 2700X would get 15200 with 100% scaling.

Considering this is bound to be clocked at least 1GHz lower when all cores are active and 100% scaling is impossible I say good fucking work AMD

32 cores score 5500-6000 so I don't know about 64 cores

8x 2700x would also eat like 600W too

8700k gets 279 fps 2950X only 278 hahah BULLDOZEN

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Why can't AMD's radeon department get their shit together like the cpu division did?

Because their focus is on Navi

Because AMD cut funding to Radeon in 2014 to focus on the CPU side, thankfully for them Sony decided to help improve Navi and most of its funding came from there, anything between that was left underfunded.

what's the GPU here? At that framerate range it seems like there's a GPU bottleneck. Although at that framerate it doesn't really matter unless you fell for the 240hz monitor meme

shekels my dude. Don't forget that AMD is an order of magnitude smaller than either of them. They're punching way above their weight. It's just that Zen is a massive, ripe goldmine

AMD would need to increase IPC in cinnebench by 20% to get this score at current EPYC clocks, that would imply a massive scalar FP unit which they could have rather used for SIMD instead.

now do the same with a high quality stream

Streaming is antisemitic.

>Zen is a massive, ripe goldmine
THE MADMAN DID IT

based and redpilled

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> renting a digital video
It’s anything but antisemitic.

Ok this is epyc

it clearly says >=512mb
maybe 512 for the "worst" rome chip?

Yeah let's use 28 core ringbus dies that are very expensive to manufacture because they scale like shit and then glue 2 of them together so that we can also introduce more latency and sell them for $20k. NOW WE HAVE SHITTY RINGBUS THAT SCALES LIKE SHIT PLUS EVEN MORE LATENCY

BRAVO INTEL

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