Compared to its 10nm FinFET process, TSMC’s 7nm FinFET features 1.6X logic density, ~20% speed improvement...

Analyst and tech writer with some clout, Ashraf, spoke with a TSMC rep and reported that.

>1.6X logic density
With clock and power gating heavily utilized to control thermal budgets/power dissipation, and a lack of consumer usage models that are CPU-throttled, this is less interesting as compared to...
>~20% speed improvement and ~40% power reduction.
Those are much more impressive numbers. I wonder if 7 nm marks the crossover to strained SiGe channels for TSMC? I wouldn't think that simple feature size scaling would result in such a huge performance boost at those scales.

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So the red is the gate, and one of the green ones is the channel? If so, is that gate's channel the one that I marked A or B?

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As of yet TSMC hasn't done any public bragging about how great their 7nm node is in detail, but they usually have a little trade show of their own each year. They'll spill the beans eventually. They gave a ridiculous amount of detail about their 16nm and 10nm processes.

A and B are two separate channels. That fin is patterned to have two gates in it.

So are the long channels just for Vcc and ground or are they used as logical inputs and outputs too?

Not sure I fully understand your question. The full length of the channel section between source and drain contacts is optimized for a host of different characteristics.
The layout there is likely just some random test logic used to check how uniformly they were building their fins and estimating yields.
You can often find two or three or more transistors all linked together in a cell, be they pmos or nmos gates.

Why are the Chinese masters of technology?

I mean this thing. What is it, what function would it serve on a logic gate, and why does it look like there are 5 transistors attached to it?

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They're good at making tiny things with their tiny fingers.

I mean, maybe it isn't electrically conductive (doped I guess) all across, I don't know.

Yeah, now I realize my question didn't make any sense.
Are the connecting vias supposed to be introduced above that stuff? Must be even tinier than those structures since doesn't look like there's much space left

I see what you mean. I'm not sure what that common rail is in the pic, it could be any number of things.

Functionality testing few new feature sizes is usually done on SRAM cells, for several number of reasons (their majority share of on-die real estate, their simplicity, etc.). Given how TSMC's short press release (linked in OP) specifically mentioned attaining double-digit SRAM yield, my guess would be that the image is of a portion of an SRAM array examined just above metal layer 1 (i.e., the metal layer in direct contact with the FETs). They could be full or half-cells, depending on how TSMC tests functionality. Pic related is an SRAM mask layout for comparison.

For most of recorded history, vias were connected above the source/drain and offset from the gate. Regarding the later, due to pitch scaling at such small length scales, this has been replaced with vias that contact the gate directly above it. Generally speaking, vias are made as large as feasible (note: FEASIBLE) so that they can handle as much current as possible. Vias that are too small can lead to severe electrostatic migration issues, current crowding, and other deleterious effects.

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Do you happen to know how cross section images like pic related are produced? I've always been curious, since I imagine mechanically cutting the chip would just destroy everything

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Sure thing. So, there are two ways to make a cross-sectional transmission electron microscope image (TEM).

One: Dice (literally using a dicing saw) up a semiconductor into pieces small enough (~1 mm x 1 mm) to fit in specialized milling equipment. Those pieces are sandwiched together using special glue/epoxy, ~four to a stack, with the area you want to image directly in the middle of the stack. You go through mechanical polishing by hand for a few hours down to ~60 micro thickness, then into the specialized machine that uses energetic argon ions to mill the rest of the material in the middle away until a (literal) hole appears. The area for several hundred nanometers around that hole is ~100 nm or less in thickness, and that's where you image (a physical requirement to do TEM is samples that thin).

Two: FIB (focused-ion beam) milling. This is the industrial process that any reverse engineering report/fab. company uses, as it allows precise location of the feature(s) you want to image. A scanning electron microscope (SEM) is used to find the feature(s), accurate down to the nanometer length scale. The top area is coated in protective material, usually something like platinum, and then a progressively thinned cross-section of material is milled away using energetic gallium ions. The region is thinned down to ~100 nm or less, and then the bottom is milled away, allowing for free release of the sample and transfer to TEM for imaging. Pic related.

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TSMC's 7nm is way behind Intel's 10nm. Even their 5nm couldn't catch up to Intel's 10nm

I wouldn't make those statements until we get releases at IEDM. Then, and only then, can Intel regain it's title.

Intel's 10 nm was/is a cluster fuck from top to bottom, hence the extended delays. Intel's 7 nm was/is in a much more stable position. A likely more accurate statement is that Intel's 7 nm will be ahead of TSMC's, given that Intel is also the only company that actually maintains (to the strictest degree possible) geometric pitch scaling, as opposed to labeling whatever they feel like "10 nm" or "7 nm," which is what every other fab company does.

>shilling this hard
intel is over, face it

intel's 7nm process is also not going to be anywhere until the 2020s, when every other leading edge foundry will be on yet smaller nodes, potentially even using GAAs.
Early 7nm is also going to be leap frogged by 7nm lines with the inclusion of EUV, so speculating about intel's many years down the road future plans is pointless.

Theres also no reason to believe intel's presentations will include any factual information on key process metrics. If they really did increase with MMP and CPP as Charlie from S|A wrote then nothing from their marketing department is worth a damn.

>just HODL bro, Su-bae will save us from this onslaught r-right????

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>muh stocks
Intel had to publicly announce, in the end of 2018, that they were going to invest another billion dollars to get their 10nm lines back on track.
Back on track would mean their 10nm facilities would be producing chips back in 2015. There is no getting back on track for intel. They're going to have nothing of consequence until 2H 2019, high clocking larger die parts will likely have single or low double digit yield well into 2020.

Tech illiterate analysts jumping at every little headline are never an indication of anything. Intel flat out will not be delivering mainstream 10nm product in any volume until well into FY 2020. Big fat king Punjab Murph himself cannot do anything to change this reality.

>Shilling.
Nigga, do you know how to read?

>Paying attention to marketing ever.
That's why I'll stick with IEDM for metrics. Granted, IEDM will always showcase the highlights of a company's work, be it TSMC, Samsung or Intel, but at least it's somewhat more bonafide. Somewhat.

That said, from a research perspective, the switch to GAA nanowire FETs is a large technological leap. Given the difficulty in realizing uniform non-vertical GAA FETs, I'd assume that most companies will make the switch to vertical GAA nanowire FETs. This also takes into account the difficulties in maintaining necessary current densities for single, lateral nanowire FETs, resulting in the stacked nanowire GAA FET solution that is even more complicated to uniformly fabricate than the singular device. I think yield will be a huge driver of which (lateral vs. vertical) technology is adopted. Either way, such a switch would require sizable investment in terms of fabrication facilities (capital). If we're talking vertical GAA FETs, only Samsung seems poised to make such a switch, given their current V-NAND technology. Given the above, I think GAA technology will be a large industry bottleneck, and will likely result in no major player releasing GAA-based technology into the market with a substantial lead time against the others.

Regarding Intel, you're absolutely right about 10 nm being a complete cluster fuck. They've known it for a long time, and they've struggled to get out of the mire they've been stuck in. They know they've fucked up, and they should be counting their blessings that they had other avenues to fall back on to get their 10 nm back on track. If their current yield improvements continue, low volume in 2019 might be feasible. We'll see what the fab. environment looks like at the time, but while I'm a big supporter of the role that litho has played in enabling continued scaling, I think we're in a regime where fundamental device physics has become king.