>Intel's next major CPU microarchitecture being designed for the 10 nm silicon fabrication process, codenamed "Ice Lake," could introduce the first major core redesign in over three years. Keen observers of Geekbench database submissions of dual-core "Ice Lake" processor engineering samples noticed something curious - Intel has increased its L1 and L2 cache sizes from previous generations.
>The L1 data cache has been enlarged to 48 KB from 32 KB of current-generation "Coffee Lake," and more interestingly, the L2 cache has been doubled in size to 512 KB, from 256 KB. The L1 instruction cache is still 32 KB in size, while the shared L3 cache for this dual-core chip is 4 MB. The "Ice Lake" chip in question is still a "mainstream" rendition of the microarchitecture, and not an enterprise version, which has had a "re-balanced" cache hierarchy since "Skylake-X," which combined large 1 MB L2 caches with relatively smaller shared L3 caches.
Incentivizing altcoin CPU mining on Cryptonight using L1/L2 cache?
Joseph Diaz
“Being designed for 10nm” means it's still not here. Enlarging cache sizes is yet another stopgap.
Adam James
>9900k is an overpriced housefire >Ice Lake Do they realize the irony?
Brandon Powell
They're supposed to have 3D die stacking by 2016 and that hasn't happened yet. If they could get that done, they could add even more cache.
Hudson Diaz
While increased L1D$ and L2$ is very likely, Geekbench always reports them wrong.
Gabriel Lewis
Intel dropped 10 nm plans for now. Either they are going straight for 7 nm or re-trying after the restructure. A lot of lay offs in any case and market will not react nicely.
In the end Intel has Jim Keller so I'm not worried.
Gavin Rodriguez
Intel denied the rumour that 10nm was dead.
Josiah Davis
>slapping on some more cache memory >major redesign...
Process technology is iterative, you don't just develop a working 7nm process when your 10nm is a massive failure, and it took you years to unfuck 14nm. Their 10nm line is going to have relaxed pitches so they can actually start producing dies with marginal single digit yields. It won't have the area scaling they targeted, it won't have the power reduction they targeted, its likely that it'll never clock as well as 14++, but thats what they'll be delivering.
The situation with Keller isn't going to do them any good. He wasn't hired on to design core arch, he hasn't been moved there either. He isn't a process engineer or anything close to it. He can't fix their foundry business. He was hired for SoC integration; hes working on back end fabric, probably the successor to QPI. QPI was originally intel's equivalent to HyperTransport. They'll undoubtedly want more feature parity with AMD's Infinity Fabric for future chips so they don't fall miles behind in scaling potential.
Intel did PR damage control over the very real truth that their 10nm line as the originally presented it is 100% canceled. That isn't a rumor. They have a completely different process and they're calling it the same thing for PR sake. The S|A article is nothing but factual archive.fo/G1nnG
Thomas Moore
>10 nm Fake news.
Andrew Thomas
Well yeah? Ofc they deny it. They have postponed it numerous times by now, and in july finally they said 10 nm not until end of 2019. It's pretty clear they are having fab issues.
Now we have a _major_ corporate restructure add to that, with the classic punch lines that nothing is happening or wrong.
I'm not saying they are abandoning 10 nm, but that they are canning the plan/roadmap and moving people around to start again. Also see the Jim Keller snatch.
The writing is in the wall and now we are starting to hear confirmations from inside.
While I don't like Charlie, it's not like he hasn't got a perfect track record with shit like this.
Andrew Hall
Keller could have been snatched to gimp AMD, also he has a lot to give after AMD success.
It's a conflicting hire in any case and they must of have given him a serious package.
Brody Lewis
>Implying based Jim Keller isn't just in the second phase of his contract with AMD; sabotaging Intel from the inside and getting paid by both companies for it Get ready for the 100-stage pipeline
>the first major core redesign in over three years >L1 from 32kb to 48kb >L2 from 256kb to 512kb
wow! it's fucking nothing. Intel feeding new info to the media to take some of the heat off the humiliating 9 series release
Brayden Lee
Snatched? Keller's employment contract was up with AMD. He wasn't brought on as a permanent hire, he was paid to work on only a couple projects, and left when they were finished. The high level core arch for Zen was finished and work on Zen2 had already begun before Keller departed. Its not like intel poached him while he was still working there. Given his track record and how he moves around the globe I don't think hes the type of person content to ever settle down with one company.
They're writing about it because it has some small implication. When it comes to caches larger ones almost always have lower latency. You don't ever want to increase latency unless you can justify it by having the average hit rate high enough, keeping more instructions there so they don't fall through the hierarchy or end up getting reissued which wastes cycles. It might show that there are some other changes in the core arch which would produce higher IPC. Just adding cache doesn't solve anything unless it can actually justifiably be utilized. Though that is a big stretch to write an article off of that one tidbit. Sites are all desperate for clicks. What can you do?
Dylan Garcia
Well, I appreciate you taking the time to explain possible implications for IPC improvements or something.
Aiden Cox
Yet Smeltdown is still implemented kek.
#AMDnovulns
Ryder Reed
When do we hire Keller to do the ground work for a FOSS CPU?
Benjamin Gutierrez
When you have millions of dollars and a compelling sales pitch for recruitment.
Jayden Martin
So Keller is like a teddy bear with microphones in it that is passed around...
Low level techs have insane contracts that restrict working with competitors. Keller is a major and competent tech on the field. FFS he was brought to AMD to design Zen and had the title "CVP and Chief Architect for CPU Cores".
History books will show how Keller brought AMD from the swamp to compete and win Intel in Zen era.
Don't downplay this hire for Intel.
Asher Hernandez
When he was rehired by AMD he oversaw the Zen and K12 design times. Dozens of lead designers each, an army of technicians behind them all. Because he was hired for that. Intel hired him to work on fabric, something else he has experience with. He was one of the people who developed the spec for HyperTransport.
I don't know why you're trying to make it seem like this is something more than it is. Intel didn't hire him to work on core arch.
David Wood
>Intel didn't hire him to work on core arch. I never said that. I implied that getting Keller was a good thing just for his knowledge of internal AMD state/matters.
You just know they've run out of ideas when they double the cache. It's a relatively straightforward way to boost performance but with thermal and die size tradeoffs, so it looks like Intel is in a deep shit with Ice Lake's performance - the arch hasn't moved forward and the 10nm process has lower performance so they're doing everything they can to make it at least as good as 14nm. It's not without precedent either. they did the same thing to Itanium so it would appear to outperform their own Pentiums and Xeons.
>still can't fab anything bigger than a 2 core with dead GPU Wew
Levi Flores
Very fast. Whether the rumors are true or not, that tweet was pure damage control. They don't control the situation anymore and can't pull off "we don't comment on rumors" line because they aren't as mighty.
Hudson Robinson
>Process technology is iterative. Yes, to an extent, unless it's the introduction of a new design feature. Note that we're talking about front-end (transistor/below ML1) design features here, so this includes things like the gate stack (e.g., gate insulator, multiple and various diffusion and adhesion barriers, work function metals, fill metals), source/drain contact schemes (e.g., source/drain epitaxial (re)growth, heavy B/P doping methodologies, Ge content increases, silicidation), etc.
That said, both Intel and TSMC work in parallel on their upcoming nodes. Within a given company, there are separate groups working simultaneously on the more pressing 10 nm and 7 nm nodes (naming convention here is irrelevant, the two nodes most close at hand to high volume), and then another separate group working on the "what's next?" questions for 5 nm as well. If they're all well organized, information can be shared between groups (need to know basis) as well as the learning from the current production nodes. If they're not well organized and managed, you have what happened to Intel's 10 nm group.
>Relaxed pitches. I mean, how often do you use minimum feature size for logic? The biggest impact that feature size scaling has on transistor density will always be with respect to cache, since (a) an SRAM cell is of a fixed, known design that will be uniformly repeated (barring any alterations to the fundamental design for LP operation, etc.), and (b) the amount of on-die real estate that cache takes up is huge.
>Power reduction. I think this is the bigger factor here. Given that operating voltage scaling has gone out the window for some time now, the loss in power dissipation scaling and commensurate increase, however minor, in clock speeds would be a big blow.
Chase Gutierrez
>major core redesign >still includes all the vulnerabilities lmao so much for a redesign >first major core redesign in over three years Oh, so it's not really a redesign since the last microarchitecture change was like 10 years ago.
Ethan Bennett
>Expecting the Jew to close the backdoors they left open for the NSA. You really can't win these days.
Ryder Campbell
>all these amdrones scared and shook as fuck when intel pays off tsmc's 7nm designs
Ryan Ross
>first major core redesign in over three years. But Sandy Bridge came out 8 years ago.
Logan Martinez
>in over three years But that would imply it getting released now, since Skylake was released three years ago. And even if 10 nm were here -- which it isn't -- they'd release the Cannon Lake refresh first. It's difficult to imagine Ice Lake being released prior to 2020 even in the best possible case.
>major core redesign >major Sure hope they're planning to do more than enlarge the caches to fit that bill.
Parker James
>The L1 data cache has been enlarged to 48 KB >The L1 instruction cache is still 32 KB in size >the L2 cache has been doubled in size to 512 KB Meanwhile, the A12 uses 128 kB L1D and L1I, and 8 MB L2, and get IPC accordingly.
>MAJOR core redesign OH BOY THIS IS INTEL'S SEKRIT SAUCE BOYZ
MOAR CACHE
James Miller
Increasing cache is not a fix-it-all solution to every CPU bottleneck. A larger cache means higher access latency, which is something you absolutely want to avoid with low level caches. Also, power consumption.
Ok, let's make predictions. 14nm++++, 200W, barely any performance gain except a few specific apps, 1000$ for a 10 core, because have to compete with zen2.
Robert Bennett
>L2 cache has been doubled in size to 512 KB, from 256 KB >2MB L3 per core
Bless AMD for giving you all the L3 even on a 6 core.
Brody Perez
I thought that's what we're seeing right now?
Connor Sanders
On paper, it's great. But only on paper.
Jaxon Cooper
If I'm not mistaken, Keller paved the road up to Zen5. Maybe he's just switching companies every five years, to milk them off. But to be honest, I think even him thought 10nm was real.
Joseph Rodriguez
*NEW* Cache doesn't matter!
Zachary Butler
Will the list ever stop growing?
Brayden Cruz
*NEW* List entries don't matter!
Landon Gray
>we AMD now Next Intel will create new arch similar to AMD... OY VEY... I meant OH WAIT
jim killer is working with raja koduri on GPU division
Cameron Martin
>jim "the pussy slayer" Keller: but intel you didn't hired me to make a complete new arch from scratch. Look, it says so in the this legal paper we both sign. Look! >intel: ... then we make a new contract where we double your pay... triple if necessary... >jim "the pussy slayer" Keller: Well now that you said triple my pay... My interest went up to "not so sure" mode :trollface:
It's that easy
Nolan Diaz
Oh, I get it! It'll take an entire lake of ice just to cool the damn thing.
Its the other way around. He goes wherever he wants to work on whatever projects he wants. Incidentally, it just so happens to be that the companies that hire him have a need for those things he wants to work on, and have pretty much a blank check in the form of money and patience just for him.
Much of AMD's past success is because of Keller, after AMD he went to Apple. It's A10 is Keller's doing. A11 and A12 are both an iteration and then an evolution based on lessons learned by Apple's silicon engineers by working under and with Keller.
Then he went back to AMD and oversaw Zen. After that he left for Tesla, whose AI chip is expected to see a perf increase between 500 and 2000% compared to Nvidia's Drive PX/DGX platforms. Source: wired.com/story/tesla-self-driving-car-computer-chip-nvidia/
>2000 FP/s + redundancy which is a magnitude order better than Nvidia's offering (doing 200 FP/s + redundancy)
After he was done with Tesla, he went to Intel because he wanted to work on something and his and Intel's interests aligned. He's the kind of guy who can go ANYWHERE and say "I want to work on X" and the company in question will jump to the tune of X.
Keller doesn't give a shit about money, he wants to work on the technology because he's that fucking good. If he could work on the greatest piece of tech engineering for $150k, he'd do it, even if the company basically said "we'd pay you $500k instead". Of course, no one but him knows how much he makes--but he's the kind of guy, where money is not even on his dimension. It's a complete after thought for his passion of engineering.
