How they did it?

then they hired all the h1bs who hate america

by lying. Who the fuck cares they make some metal junk a hair smaller.

100pm.

>node shrink doesn't matter!

well there's this idea of making CPUs in separated clusters wired on infinityfabric-type interconnects using bigger nodes for stuff you can't shrink well like controllers and shit and using tiny nodes for stuff you can (like transistor arrays and memory), so maybe they just focus on how small they can make the smallest components without having to shrink the entire CPU logic at once...

By constantly getting bankrolled by Apple over the years.

The only correct answer.

Apple money

>t. intel R&D

Lol
Graphine memes and under 1nm going away from silicone

Attached: intel-10nm-roadmap.jpg (700x495, 62K)

This for one. Their 5nm is probably just another marketing gimmick.

Hiring is pretty irrelevant for this shit either way, since they were an established company for awhile. They fucked up because the shareholders were fine with stagnation as long as the sales looked good. Lack of ambition basically.

Compare it to Applel who had the best mobile CPU for about a decade now but still always attempted to outdo themselves, even when the competition didn't get close.

>Intel isn't getting millions from Applel too

they actually expect we can go as low as 3nm, possibly 2nm, but it will cost way to much for consumers

Attached: 1537432326146.gif (540x674, 268K)

it just clicked that the window behind their company logo represents a wafer.
i may be retarded.

Physically impossible with silicone

What about with silicon?

it's just marketing terminology, not actually that small.
gains are still to be made after "1nm" by switching to new materials that allow the same structures to be smaller or exhibit other beneficial qualitities.

>he doesn't remember when we used um. (micrometers)

>mine is 5nm bigger
Said every Intel employee ever.

With silicone we can't go smaller than 3nm really, since a silicone atom is 2nm wide.

Silicone is a polymer much larger than 2nm.

Threadly reminder that node names are purely marketing.

The smallest feature at the 7N node is about 40nm wide (TSMC).

only 4 years of delay on 10nm. wew lad.

999picometers-

>best mobile CPU
how much apple dick have you had in your mouth

not him, but what the actual fuck are you even trying to talk about?
Apple's mobile chips were LEAGUES above android counterparts and still are in many aspects, although Qualcomm is playing catchup very well at the moment
is your hate for a brand so large that you can't admit they offered a superior chip, performance and feature set wise?
I've been using android since the very beginning (G1) and only used Apple once (iPhone 6 provided by my workplace), so think for a moment before you call me an apple shill

Good chips, bad software. Meh.

apple is a terrible company

Literally jacketman R&D shekelz.

Apple's contract with Intel are recent and they only churn out modems for iPhones.

The order is so massive that it sunk all of Intel's fabs that their CPU business had to take a hit.

it is, but that changes nothing, their chips were better and that's the end of the story unless you want to rewrite history with a time machine

Every company is terrible. Doesn't change the fact that some of them make great chips compared to others.

The change to Intel Macs isn't that recent and Macbooks are by far the best selling ultraportables and the few pcs that don't sell less and less. Modems are just an extra and probably down to their beef with Qualcomm.

Overall Intel is likely to have gotten way, way more Apple bucks than a pure fab, while starting in a better position too. Money is a silly excuse for their stagnation.

rip in pieces intlel fabs

>silicone

Attached: 1433245629113.jpg (300x300, 10K)

marketing does not real size of nanothing

>silicone

We start writing hate on the chips.

Attached: amhate.jpg (610x458, 364K)

I HATE KIKES AND NIGGERS

leather jacket man and the iFaggot shekelz

based rebel chinks

Around ~3nm, expect to see chiplet based designs across CPUs and GPUs. Chiplets will allow for a massive increase in performance per watt @ 3nm with only a moderate increase in power overall.

AMD's Rome EYPC architecture which has a 8+1 config of core/uncore on a passive interposer and the performance it brings to the table, will pave the way for the market. Simply by separating uncore from the core and tying it together via an interposer, will MASSIVELY decrease the size of a CPU die. Which means that the total number of dies PER wafer will go up considerably. This makes it so that even if there are defects in the wafer after printing (because 100% yields are next to impossible under current technological constraints), the sheer number of dies per wafer guarantees incredibly high yields.

Zen1 at 14nm had around an 82-85% yield PER wafer. 12nm I think increased that yield to 85% min and maybe eeked closer to 88% on average, PER wafer.

7nm is a double node shrink from TSMC's 16nm node, as they skipped 10 and went straight to 7. As a result, the density and power increases are around 60% greater for the former and 40% lesser for the latter. Further, TSMC still maintains a 16nm processing line, which is extremely mature (which means the causal factors of most defects have been addressed, in turn leading to very high yields there as well).

Zen2 @ 7nm is allegedly ~64mm^2. If we assume that AMD is configuring them as 2x4c CCXs as they did with Zen1 (instead of a single 1x8c CCX--though this could also be true). According to this source: en.wikichip.org/wiki/7_nm_lithography_process, TSMC's 7nm HP process has a 300mm wafer size. Using this calculator: caly-technologies.com/die-yield-calculator/, which you can assume to be a reasonable source of truth.

According to same wiki source, but for Zen: en.wikichip.org/wiki/amd/microarchitectures/zen#Pipeline, we know the following FACTS:

Zen1 @ 14nm is: ~22.058mm x 9.655mm approx.

1/2

According to this source: semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html, we can say that TSMC's 7nm chip brings about a 43.75% reduction in area over 16nm. Remeber that Zen+ is still Zen1, with some very minor fixes, a slight decrease in die size (as its a half-node decrease), and a mild increase in clocks.

We know from earlier that Zen1 was ~22.058 x 9.655mm per 2x4c CCX + uncore die. However, take a look at pic related. CCX0 and CCX1 are fairly sizeable, but the surrounding uncore is using up a SIGNIFICANT amount of die space. We also know from: en.wikichip.org/wiki/amd/microarchitectures/zen#Pipeline, that Zen's PURE CCX area is 44mm^2. Given its slight rectangular nature, given 44mm^2 we can safely assume that the width of Zen1 is 4mm and lenth is 11mm for 44mm^2.

If we know the width of the pure core CCX and know the full width of the actual die, then we subtract that pure width from the aggregate width and get:

>9.655 - 4 = 5.655mm

5.655mm is the total amount of space the uncore is using up. in the width of the CPU that isn't pure core logic. Further, we can see from pic related that a small portion of Zen's die uses uncore near the end of CCX1. If we run with 11mm for 1x4c CCX and double it, we're looking at 22nm which leaves 0.058mm for the remainder of that uncore at the end. Funny how that works out.

Given this, let's reduce the numbers by 43.75%:

>Zen1: 11mm x 4mm (pure core 1x4c CCX design) @ 16nm
>Zen2: 6.1875mm x 2.25mm @ 7nm >> ~14mm^2 per CCX, multiply that by 2 and you get: 27.84mm^2 PER die

Now, Zen2 @ 7nm as mentioned before is allegedly 64mm^2, my number is off by roughly 2x. Which is quite significant, which means that not ALL of the uncore logic likely made it off the die; things such as the I/O, the interconnects for traffic between CCXs and between cores. The L1, L2 and L3 caches likely h ave been increased as well, IFOP SerDes (w/e it is) may have been kept as well.

2/3

Attached: zen-die.png (950x417, 896K)

Of course, all my math could be horribly wrong, in which case god dammit all, I look like a massive retard on the internet. But let's assume that somehow, I'm right, just a little bit and play with numbers.

We clearly know alleged numbers and the numbers I calculated don't match, and a nice length by width to get to 64mm^2 would come out as 16 x 4; which makes the chip larger at 7nm per die than it does at 16nm per die. But let's run the numbers. I've kept the default 0.2mm for the scribe lane (horizontal and vertical, cause I can't find any sources that in some meaningful way tells me what the fuck that means):

> 22.058 x 9.655 @ 16nm @ 300mm wafers

Gets us:

- 214 good dies, 16 partial dies, and 50 dead dies per wafer which translates as an 81.12% yield per wafer. Zen was reported in the 80s for yields, plus all the process optimization involving engineering and math way fucking beyond me, AMD and TSMC somehow got their yields to mid 80s. For us retards, 80% yield per wafer is insanely good.

So then,

> 12.375 (6.1875*2) x 2.25 @ 7nm @ 300mm wafers

Gets us:

- 1634 good dies, 112 partial dies, 4 wasted dies and 46 dead dies which translates as a 97.26% yield per wafer. This is damn near magical, so we'll drop it by 10% to account of problems, revisions, new defects, and me being a retard; mostly me being a retard. So 87.26% yields.

That translates as: 1426 good dies, 98 partial dies, 3 wasted dies and 40 dead dies. Now, purely from the good dies, let's further assume that 60% of them are fantastic for desktop & enthusiast markets, which leaves us with: 570 dies that are the best fucking binned ones on that wafer. These dies can clock as high as 2.5 to 2.6GHz while sipping on thimbles of power, they can turbo to 3.0GHz and XFR further to 3.2GHz all cores. 570/8 gets you: 71.25 EYPC CPUs per wafer.

If the most powerful 64c EYPC is going to be priced ~$5500 per, we're looking at: $390.5k per wafer in sales.

3/4

According to this source: semi.org/en/node/50856

The average cost per 300m wafer is ~$300, maximumo of $400. So if we assume worst case scenario based on all information above, and most priced wafer option, and assume that the cost of packaging of the dies + uncore + transposer + testing + validation adds another 150 dollars in cost to the mix, we're looking at the cost per wafer to be $550.

So $390,500 in sales - $550 in cost per wafer, and AMD's looking at $389,450 in pure profit PER wafer. I'm no engineer, I don't know a damn thing about supply chain management or what the actual costs are at bulk that AMD gets from TSMC for everything top to bottom. But as a thought experiment for basically back of a napkin math, $389.4k in profit PER wafer, when most companies are going to be ordering hundreds if not thousands of wafers, and suddenly this number jumps to crazy levels.

1 wafer = $389.4k
10 wafers = $3.894M
100 wafers = $38.94M
1000 wafers = $389.4M
10,000 wafers = $3894M or $3.894B

According to TSMC's own capacity capabilities: tsmc.com/english/dedicatedFoundry/manufacturing/gigafab.htm

They're able to at maximum produce >100K wafers per month. But this would be spread across all its customers. Also note that the numbers above are exclusively for the 64c EYPC Rome Server CPUs. So if we consider that AMD gets a hold of 1000 wafers for itself out of a pool of over 100k across many customers, AMD's looking at $389.4M in pure profit from said CPUs alone. This does not account for gains from ThreadRipper or R3, 5, and 7 series CPUs; whose on packaging & validation costs would be negligible to its profit turnover.

This is 7nm non-EUV. TSMC will move to EUV later into 2019, leading to an additional 15-20% reduction in area per die per wafer. It would negate by ~half the reduction I did last post because my numbers were somewhat off. So like mid 90% yields for Zen2. Intel can't compete with this with 14nm+++.

When are they going to 450mm wafers?

Wafers are over $3k a pop, dude. Dopants aren't free and 28nm bulk isn't relevant. FinFET wafers are fucking expensive, so expensive that they make SOI wafers look like a bargain.

Delayed since years ago, and no one in the industry has taken major steps towards rectifying it. It would bring costs down, but none of the logistics are there. There is no supply chain for larger wafers ready. Its not happening any time within the next year.

when china dominates the industry

DO you have an alternate source for that cost? Just want to know, because typing in semiconductor wafer cost gets me 300 and semi.org also points to 300-400. So am wondering the mag order difference in price.

semimd.com/blog/tag/finfets/

Buddy, if wafers were only a couple hundred bucks people would be dancing fucking naked in the street. That figure is so far removed from reality I can only assume it was a typo lacking one 0.

Gotcha. Makes sense, thanks for the source!

Outdo themselves by gimping previous gen phones to support their bullshit performance metrics.

>Shit Mr. Cook we were only able to improve CPU performance by 50%
>Only sight performance from TSMC binning for us and because we raised clock speeds by 45%
>We have to display 2x performance.
>Oh I know let's gimp previous gen by 25% with the next update.
>They'll be eating truffles straight out of our ass and begging for next year's announcement.

By pulling arbitrary measurements out of their ass because there is no standard in measuring this shit.

Smaller logic cell size and SRAM cell size than intel's 10nm, rabbi.

this is about the smallest you could possibly get with regular matter. after this, we might just need new ISAs.

This is gonna be a good read

We're going to use black hole logic to crush silicon to infinite density and make singularity dies.
t. nostradamus

kek ive thought of this before. but think of the massive amounts of energy to make a CPU die out of that. also how would you prevent it from just sucking in all matter and killing everyone near it?

How do you prevent your own stomach from digesting itself?

Teehee!

fuck off with your walls of text spergazoid

No u.

theres mucus constantly being produced to line the stomach so that the acid cant eat at it. and you also dont have acid in your stomach all the time.

thanks for that, Jim.

Attached: 1540609357750.gif (600x600, 203K)

The wafer might cost $300 that's not unreasonable. However, that is just the bare silicon wafer that the foundry uses as a starting point. That cost doesn't include all the exposures, treatments, etc in the process of actually making the nanostructures of the finished silicon chip. Which is the hard, expensive, part.

Also, packaging the chip afterwards isn't free and is getting more complex (look at threadripper or EPYC)

This. A company will pay for a processed wafer. Its reported that 14nn/16nm from gf/tsmc cost around 6000-8000 dollars and 7nm is expected to be a bit more. Suddenly those die candidates cost tens of dollars each when there are zepplin dies being sold for 50 dollars with the 200ge athlon for example.

Jim is that you?

Attached: 1539941569931.jpg (357x434, 91K)

Moore's law never died, Intel simply killed itself with diversity hires.

Are there any reason why anyone would go below 28nm? It's already pretty small.

We are going to use closed time-like curves to get results of computations before we even start them.

More chips per die.

I mean, that's technically correct.

While it's true that a big part of Intel's problem was not trying to push the envelope, a part of that is in fact them hiring diversity hires content to sit on their asses and take a paycheck instead of doing that pushing.

Nevermind the - literal - hundreds of millions thrown away on supporting diversity bullshit.

Are you kidding?
28nm HKMG bulk is beyond trash tier in comparison to industry 16/14 FinFET. Cost is the only thing that would dissuade an IC designer from targeting a FinFET process, and even then 22FDX and upcoming 12FDX and 18FDS deliver massively lower power/higher clocks while being price competitive with older bulk nodes.

Global Foundries had preliminary results with 14LPP that made planar bulk silicon processes irrelevant even for tiny low power ICs. Die area reduction is over 70%, reduction in leakage over 70%.
Once 14LPP was in production they had better fmax than their preliminary results. Their 12nm process is built on the same back end of line with a new track and transistor library, and they got about 10% lower power and 10% higher clocks from it. In comparison 28nm leaks like shitty garden hose and can't reach clocks half as high at iso power.

don't you mean wafer

Are they going to work on 450mm wafers for 28nm?

450mm wafers are still on eternal hiatus

Yeah I misspoke.
>Are they going to work on 450mm wafers for 28nm?
No idea, it just seemed like common sense to me - doing more with the same amount of material.

So just like EUV, non-copper/alluminum BEOL, or non-silicon substrates. Sad really

Except EUV is already in use.

>So just like EUV
t. intel

Micro black holes don't have the stability to exist for long and grow. If they did, our solar system would be gone years ago from particle collision experiments.

This guy knows

If you somehow could shrink a CPU die to the size of a black hole it would have the same gravity as a CPU die - next to none.

No you don't get it, you use the black hole to crush the chip to infinite density.

So, to a black hole?

No, to singularity. Do you call the pre-big bang singularity a black hole?
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

FUUUUUUUUUUUuuuuuuuuuuuuuuuuuuuuuuu

Attached: 1534941054268.png (400x400, 91K)

Cell size doesn't matter

EUV is already in production for certain node lines at TSMC, Samsung & GloFo. Its just not actively being pursued by the mainstream chip makers such as AMD, Nvidia, Apple, etc, because its still too risky and the tech itself hasn't matured enough for full scale adoption. A single defect can fuck up the die.

7nm does not use EUV mainstream yet: semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html

However, 7nm+ is expected to:
>7+: 15% to 20% reduced area

Currently, and universally, we use ArF Immersion methods for our lithography: en.wikipedia.org/wiki/Extreme_ultraviolet_lithography

Which has a wavelength of 193nm. That's super fucking tiny to the human eye, but its friggin' massive compared to EUV, which has an actual (in small scale production) wavelength of 13.5nm. This means that when printing the design of a chip onto the silicon, you can cram WAAAAY more transistors in the same area despite still being on 7nm. As mentioned earlier, TSMC expects a 15-20% reduction in area.

Zen2 will be 7nm TSMC, its possible that AMD might move Zen3 out to 5nm and put out a Zen2+ to take advantage of EUV process, couple it with the 15% reduction of area (min) and do what they did from Zen1 to Zen1+ on the same fabrication process.

Instead of relying on a half-node shrink, they'll just use the newer technology, which can print MORE transistors for the same area because the wavelength at which the circuitry is etched is now significantly more accurate.

If Zen1 was 80-ish % yields, and Zen2 ends up say 87% yields, then EUV will push Zen2+ into 90-92% yield. Further, it will give AMD a good idea of how EUV affects their Zen architecture, what kind of binning they can do with it, how far they can safely push clocks without power and voltage increasing exponentially, the kind of heat and failure rates, etc. Vast amounts of critical information, that will get poured into Zen3 @ 5nm EUV.

Zen3 will be Intel's worst nightmare.

I think that's why they hired Jim Keller to work on SoC & Fabric. Intel's leadership might be glue eating retards, but some of their engineers in their R&D labs (not their fabs) are smart as shit--they KNOW where AMD is going with Zen. TR & Gen1 EYPC are chiplets. This the beginning of the end if they don't adapt and adapt quickly.

Its why their marketing put out that sloppy hit piece about how AMD is "gluing together dies". They also know that EUV is on the horizon, which is going to be a revolution in how chips are fabbed. Intel had likely hoped to get their 10nm out the door before EUV hit, so that the node difference betweeen 10nm and 7nm wouldn't be significant and then they can pile on EUV and close the gap to

Fun fact:

>Illumination: Central angle 6 degrees off axis onto reticle On axis

Source: en.wikipedia.org/wiki/Extreme_ultraviolet_lithography

If you google the Illumination statement and look up images, you get pic related

Source: researchgate.net/publication/253360255_Incident_Angle_Change_Caused_by_Different_Off-Axis_Illumination_in_Extreme_Ultraviolet_Lithography

>This incident angle will affect many things, eventually to the line width. Shadow effect also strongly depends on the incident angle. This shadow effect in the EUVL mask is an important factor that decreases the contrast of the aerial image and causes a directional problem, thus it will make line width variation. The off-axis illumination (OAI) will be used with conventional on-axis illumination to make much smaller patterns. This OAI will split the main beam and change the incident angle. We found that if the incident angle increased with higher degree of coherence, the aerial image went worse

What does this mean? At a very high level, it means that traditionally, when etching a die onto a wafer, the pattern that's microned by the lens AND the laser itself needs to be EXACTLY ON FUCKING POINT, or the etching will go wrong and your die goes straigh into the trash. Which is extremely expensive.

The Illumination angle above suggests that there can now be an error margin of up to 6 degrees during the development process. That's a significant margin of error where you can print a die on a wafer, have a slippage somewhere in the chain and as long as its within that 6 degree angle, your die is still good. It may not bin as well as some other dies on the chip which means it might run a little hotter or it won't clock as high or its baseline voltage is a bit higher, etc.

BUT, its not going into the trash. Compound this across many wafers and your yields goes up another few % points. Which is huge for cost/loss and gains.

Attached: On-axis-and-off-axis-illumination-With-off-axis-illumination-diffraction-orders0-are_Q320.jpg (320x320, 12K)