RIP INTEL

based Chinese

Hopefully by then it's dead and bankrupt

TSMC 7nm is ahead in density compared to intel's 10nm.
TSMC is following ASML's node definitions faithfully.

>talking out of your ass this much
What makes you faggots do this?

>Taiwan
>Chinese
Kill yourself faggot. Never associate my people with chinks. Don't bother @ing me.

>What makes you faggots do this?
Anonymity.

ASML can an hero btw. I'm talking purely technical/theoretical.

You're talking purely bullshit.

have a (You) good sir

The Taiwanese are a small people, they will make it work

Explain why he's talking bullshit. Your post is as useless as his post.

quints

shhh

Even at 3nm it will probably still be a double digit size in reality. When they actually go down to single digit nanometers, they'll already be naming it in picometers.

Because many front end feature sizes are in fact approaching the etch resolution of these processes regardless of the fact that they aren't named for it.
Some user started posting a little info graph comparing the MMP and CPP of different process nodes, and blithering retards who have no idea what they are have been repeating numbers they don't understand ever since. A 40nm MMP does not mean that a 40nm feature is the smallest on chip, it is the exact opposite. This is a back end of line feature that influences area scaling.
Look up any Chipworks dissection of a recent chip.

You have no idea how process names are even determined.

So where can we learn this shit to an adequate level so we can be as insufferable as you?

IEDM, other industry presentations like SEMICON West, you could just read watered down semiwiki articles that aggregate all that information for plebs if you wanted to be lazy.
For intel's 10nm process, their trigates have a nominal width of 7nm at the top of their fins. Right there there is an etched trench where the fin is grown and it end up smaller than the node name. Wow. Jow Forums BTFO forever by intel who is trailing TSMC in total density. Imagine that?

Intel is fini...

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>construction will begin in 2022
>begin

they are pricing in intel reaching 10nm in 2019

Here, since I know you're all too retarded to function:
semiwiki.com/forum/content/7191-iedm-2017-intel-versus-globalfoundries-leading-edge.html
semiwiki.com/forum/content/7443-top-10-highlights-tsmc-2018-technology-symposium.html
semiwiki.com/forum/content/7544-7nm-5nm-3nm-logic-current-projected-processes.html

Have fun learning something.

Why did I even laugh at such a stupid joke fuck

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>tfw intel will become irrelevant in your lifetime and the world will become a jewless paradise
Feels good man.

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Intel is another stockholder's darling, similiar to Nvidia before it got fucked. Watch the true meltdown happening once Zen2 is going to assrape them at full force. Those stupid shareholder fucks truely believe Intel delivers highly competitive 10nm chips in June 2019.

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No. IBM has successfully produced 1nm transistors.

3 is 5, 7 is 10 (when comparing TSMC to Intel).

>chink in denial

The goyim knows! Shut it down!!

Witnessed

tsmc 7nm is smaller than intels 10nm... so no its not equal

In which parameters is it small?

overall its around 15% smaller in total

It isn't but you can keep telling yourself that if it makes you feel better.

>isn't 3nm factory too small to produce anything

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The ethnic groups are the same you false flagging shitposter. Taiwan even considers itself the 'real china' because their government is even called the RoC. No actual Taiwanese person gets mad when they get called ethnically Chinese.

this is comparison before intels 10nm got 10% nerfed

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DELID DIS SIR

>MTx/mm2 higher than everyone else
I wonder what he meant by this...

>MTx/mm2
thats before the 10nm was crippled

It'll be late but the process is still superior to TSMC's.

Nope, the jews will just infiltrate TSMC if they haven't already.

>SRAM density lower than TSMC N7
>total logic cell density lower than TSMC N7
>TSMC N7+ improves on density even further giving it another 15% area scaling advantage

Intel's 10nm node is less dense. You can't get around this.
No. No its not.

>process is supposdly superior
>cant produce high clocked parts
>will use 14nm for the "high performance parts"
Ok :)

>jews will just infiltrate TSMC
Xi will stop them

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You don't know about the jewish influence in the Chinese government, do you?

"""1nm"""

well played.

t. retard

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That was a good chuckle.

oh fuck, witnessed.

Emperor Xi does not yet rule the rebellious province

what am I looking at here? the broken image links?

You specifucally choose the date of amd being at highest point to make it look bad, aren't you?

>not yet
he never will.

TSMC's 7nm EXISTS. Intels 10nm is not, thats why it was revised to something like 12nm. i bet it's still slower than 14nm++++++++++

At 3nm quantum tunneling will render the chips dysfunctional at frequencies beyond 1ghz.

The yields could be problematic too.

Silicon simply does not behave well below 10nm.

It's okay, they're calling it 3nm but really it's like 32nm

I'd fuck her.

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>2023
*yawn*

aggressiv timeline from TSMC but not for "us" consumers.

looks like a bunch of flies swarming

bless you, haven't laughed at a post this much in a while

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can we go under 1nm?

soon

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Those are just names, not actual sizes.
IIRC "14nm" uses something like 50nm transistors.

Only in countries that use metric.
If you use imperial you are fucked.

Could it be that AMD were right all along by producing many cores that have no more than 1ghz in power?

for intel, yes

only if you employee 100% chinese

came here to post this.
fucker.

i want to work with asian qties ;_;

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Not even close, my guy. Look up intel's IEDM presentations, Global Foundries presents there as well. TSMC has tech presentations of their own. Cadance has published material on various processes as well.

CPP and MMP are not front end features. The FEOL is not larger than the BEOL. Jesus.

The fin pitch on GloFo/Samsungs 7nm process was either 30nm or 27nm based on what they shared back at IEDM 2017. That means the distance from the furthest edge of one fin to the start of the next, including spacing. The fins themselves are incredibly narrow. As already stated ITT, intel's 10nm process node produces 7nm wide fins.
This board is just too retarded to help.