Rate my datapath

Rate my datapath

Attached: DATAPATH(2).png (1541x968, 75K)

>Implying 95% of Jow Forums knows anything about computer engineering

sad

4/10 unless i know more about your predictor, ISA, forwarding and ALU.
Immediate issue: wasting too many 'CLKs on getting your data into your ALU
This is too high-level view for valuable feedback. Give more details.

2 bit saturating-counter predictor, forwarding unit is trash, the ISA is a reduced mips version and in the alu there are logicals, shift unit, booth multiplier non restoring divisor and a carry lookahead adder

i just want an aesthetic feedback don't worry

ugly

Attached: BBASIC_QUEENS_DIAGRAMM_B.png (390x443, 35K)

Without an implementation everything is bullshit/fantasies. Basically the devil is in the details, and one huge detail you are missing is the blank blocks where your memories/caches go. I will also note from personal experience that if your target is a fpga register forwarding is easy in simple designs, but much more difficult in bigger designs. Unaligned memory accesses were more complex than I expected. Finally if this is ultimately a non toy design that accesses external sdram, caches really matter. Basically the cpu pipeline itself is the easy part.

Beyond that, looks ok. Try to get it in a fpga and hit 200-250MHz. 200MHz in a Xilinx Artix 7 would be good imho.

>logic design
so fucking boring. also,
>physical designs
It's much more easier and efficient to use verilog

What's your goal here? It seems like a basic solution to a basic assigment. Unless i see your VHDL, i don't really have anything to critique (assuming you're undergrad).
Aestheitically alright, i like the explicit denotion of F/D/X/M/W, but it sits at a very weird place structurally - why the emphasis on muxers before ALU? Why separate bpu, but put the gate for branch/error into the mux? There should either be a few more "boxes" and a lot less other "shapes" or the other way. It really sits in a weird spot.
It doesn't seem clear to me which part of arch it wants to emphasize.

Case in point: pic related wants to tell you about branch prediction.
There's no useless bullshit around, but it's not overly specific either, just the right level to explain "this is how branch prediction works in general".

Attached: bp.png (712x344, 34K)

it was a semi-custom design, i lost the images about the physical implementation, so whathever
yeah there isn't any goal in this, just to make a vhdl functioning processor that could do a qsort

Speak for yourself fag. I design nuclear reactor cores. This compsci is wayy too easy for me.

>just to make a vhdl functioning processor that could do a qsort
Then i'll assume you have some hard requirements and came up with this overkill design as a result. You'd get points for this from me if your goal was to make a simple RISC-y design in VHDL.

Nice circuit

Fuck off mate, I know you're trying to trick us into helping you with your homework

Well if you do enjoy doing forwarding units in your free time i won't stop you from doing it and posting it here

Right now you are passing the B register though a pipeline to a tri-state-buffer. Can't you make an ALU-bypass that passes A directly to the result register (or do A+B with B=zero) and have the data go from result to memory? With this you can remove a register, the control signal to it and simplify the right-most tri-state-buffer as it doesn't need to be bi-directional anymore. Or do you control the data memory addressing through the result register?

Attached: 1547247012960.png (1541x968, 80K)

I'm not sure if i'm getting this correctly but the bidirectional bus is the data bus and the one directional bus is the address bus, which is controlled by the alu results as the address is computer as reg + offset, while the data to be sent is a value in a register and do not need any operation to be done

Does the memory have to clock in the address before it can clock in the data (2 clock cycles) or can you put both the address and data on the busses and write it in 1 clock cycle?

I put them in the same clock cycle

Right now It takes 3 clock cycles to write data. On the first cycle you populate A and B for address. Next, A and B go to result and your data from register file goes to B. The next cycle, B goes to pipeline (B) while the result has to remain unchanged (waiting). Only then on the 3th cycle is the result put on address line and pipeline (B) on the data line. You are better off creating a 3th register called C. This way you only need 2 cycles to write data and you can neatly pipeline memory writes, one after the other. This will increase performance significantly and will speedup your sorting.

Attached: 1547247012960.png (1541x968, 79K)

Wait a sec i use b as data , a + imm for the address (imm comes from the instruction word)

>design nuclear reactor cores
It's simple thermodynamics, the only difficult part is all the government regulation. You're basically a glorified HVAC designer.

You need the B register twice. Once for the addition with A and once to get data to the pipeline-B. At the same time that A+B=result is performed you put data from register file to B so that it can be put to pipeline-B.

If you can put your data to a 3th C register as explained above you can pipeline the entire thing and write data every clock cycle. You would complicate the register file a lot though for extra speed. If you design it for an fpga then you might need one that has a 4-port memory block, or split up the register file into two register files.

Attached: 1547247012960.png (1541x968, 80K)

I don't get it but ok, it'3 am over here aand i spent my friday night discussing on a burmese origami imageboard about old homeworks. And i really don't get the point, i don't do a+b, i do a + imm (immediate, it comes from.the instruction). goodnight

>a + imm (immediate, it comes from.the instruction)
Ow, in that case it is fine.

Oh yeah, tell me moar about simple thermodynamics when you get a sense of hadron physics famalam.

>LARP
Tell me the leading anomaly dimension of fermion in simplified Yukawa model given by Lagrangian in pic related.
It's undergrad-tier excercise that anyone with a slight clue in particle physics should be able to do in few minutes.

Attached: L.jpg (720x115, 12K)

Not worth my time, kiddo.

not him but someone else with a undergraduate Physics and I do not know the answer, can you provide an answer

God this bring me back to to the days of my first systems class, very glad those days are behind me

Browsing this thread makes me feel dumb :(

Attached: BzbFfITCYAEzBfb.jpg (362x362, 21K)

Reading this post makes me feel smart :)

Attached: J4qXoO6.jpg (300x300, 22K)