Intel BTFO

Fuck I want a 3800x.

Ice lake is already faster than zen2 fucking retarded shill.

18% better IPC at 300% lower clock speeds

Any industrial chillers involved?

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Says all of the ice lake processors that have been benchmarked and spotted in the wild?

Ice lake is basically mobile only until 2020, and until then limited release with no more than 4 cores. While Zen2 is real and you will be able to get it on 7/7 with up to 12 (maybe 16?) cores and use it in motherboards that exist TODAY.

It's not an Intel CPU.

Why would there be?
The only reason Intel really had to use a chiller was because of the retarded thermal goop under the IHS
AMD has always soldered which leads you to be able to cool a TR CPU pulling 400w with a lowly 140mm noctua cooler

it does clock to 4.6ghz user out of the box

>The only reason Intel really had to use a chiller was because of the retarded thermal goop under the IHS

yeah nothing to do with the fact that they clocked a 28 cores TO 5GHZ
no it was the ihs

for the chipset, yes

Where are my fucking XFR enabled benchmarks. 4.6 is the BARE MINIMUM of what it's capable of.

no it didnt
t. amd fan

Play the waiting game with is pajeets

The amount of jewery that will happen in 2020 will be unprecedented, even for Intel.
when enterprise customers order the newest intel CPU server thinking they are getting ice lake and instead get crappy cope lake SP (40ish core?) 400W abomination due to supply issues they will never go intel again.

>ice lake
>faster
HAHAHAHAHAHAHHAA. maybe 3-5% IPC overeall, 2021 desktop JUST WAIT PLS

>ice lake
>it's actually boiling
What did they mean by this?

10nm server cpus are coming in 2021
no one in 2020 is gonna buy a xeon cpu simply because they cost too much and draw double the power of epyc cpus

Have there been any zen+ vs zen2 benchmarks for floating point specifically?

>shitdozer
>higher IPC than SB
lel
AMDrones are 12yo. Shitdozer had worse IPC than phenom and you had to OC to housefire levels and still lost to stock SB.

O shit that's lower latency than my haslel
Finally time to upgrade

INSTRUCTIONS PER CYCLE

>yeah nothing to do with the fact that they clocked a 28 cores TO 5GHZ
>no it was the ihs
I'd be willing to bet it was the IHS and the TIM under it that facilitated needing a chiller
The chiller was merely there to get coldplate and IHS temps low enough to facilitate better thermal transfer across the paste, if Intel just soldered they wouldn't have needed a chiller just to do a few suicide runs on cinebench

Exactly
AMD fanboys deeply disgust me
and thats coming from an AMD fan

you think they used TOOTHPASTE on that abomination?
are you retarded?

what about the 2x 1.2kW PSU it needed?

>Latency fixed.
>Mfw this just keeps on getting better.
Like a gift that keeps on giving and it's not even out yet. I can't wait to see how well it really overclocks. Apparently we're getting that info around E3.

pcgamesn.com/amd/ryzen-3000-cpu-overclocking

>We quizzed AMD’s Erin Maiorino about the overclocking potential of both the Ryzen 3000 CPUs and the X570 chipset as a whole
>The somewhat cryptic response was: “No, no comment on that just yet… in ten days, we should be pretty good.”

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>4000mhz
Enjoy your $500 mobo and your $300 ram.

Soon...latency doesn't matter LOL

They fucking did
techpowerup.com/248567/intel-xeon-w-3175x-to-lack-stim-retain-thermal-paste-for-ihs

I don't think AMD is in any position to post deceiving benchmarks, 3900X will really beat anything Intel at single threaded stock speed.

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checked

also checked

I don't doubt that at all. Even at stock this thing is a monster.
Now if it can be pushed to 4.8 or maybe even 4.9, it will utterly assrape anything Intel could throw at it.
Can't wait to hear about the OC results. Though I don't think there's all that much room for increasing the clocks. I have a feeling these chips are operating fairly close to their limits, or at least the 3900x is.

mobile.twitter.com/Thracks/status/1134098430614093827

>mobile twitter
yikes

lmao, "muh latency" retards BTFO

How? They were right, thats why the cache is so big now

ram speeds were limited on x370/x470 due to the processor's memory controller not the motherboard. The new processors can be dropped into any of these boards.
Try : Motherboard (free). Ram $300 is better than the $400 i paid last year. Intel mobos cost more. Nigger tier ram has nigger tier latency.

Nah. Stock clocks are safe. I got a 15% oc on an 1800X, so I’d be surprised if you couldn’t get at least 4.8 out of it.

>she's Taiwanese (read Chinese)
1989 Tianamen Square Massacre

Is it me or does 4x.xx ns of mem latency seem like horseshit? That's like half what it was on their previous gen. How the fuck is this achieved when it has to hit two chiplets vs one? Something tells me that, given the new architecture, there's something goofy going on that aida64 has to be updated to account for.

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>AMD unveils 5GHz overclocking potential at E3

I own multiple ryzen setups and a kikeripper.
Stop posting memes and try some reading comprehension faggot.

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>I own multiple ryzen setups and a kikeripper.
[X] Doubt

While that's a possibility they also made the cache faster and bigger which would help mask latency. I dont think you can run a memory test that runs independent of cache so the improvements of a cache should reflect in the memory tests. But I could be wrong

Physical distance of the signaling path is the smallest part of the latency equation. There have been chips in the past with external memory controllers which had super low latency. The controller itself is the biggest component to total signal latency. Wire length at most adds 1-2ns. Its inconsequential.

It's possible with 4000mhz RAM and other tweaks like better IF

What process is X570 made in?
Or for that matter, X470?
I recall 370 was 55nm, did they move on to a better process since?

Should I post a pic w/ the thread in the background? Which do you want? The kikeripper or the ryzen?

Post everything

The chipset doesnt mean jack shit really. its just an IO expander. Current chipsets just link up via PCIe and bridge to other protcols

For Zen2 the x570 is just another IO Die (like one present in the CPU already) operating in chipset mode. So you essentially double your native CPU IO capability at the expense of just a x4 PCIe4 link. This die is 14/12nm glofo

Exactly what I was thinking. It's probably the program not having accounted for the increased cache and it bringing down the average. There's no way you can get the latency half with straight RAM access.
I'm speaking about all of the micro-architectural features the memory access has to pass through that it didn't have to in the prior ryzen. There's zero way you can cut the latency in half by adding additional latency features to a pipeline. I'm calling bullshit on this until official measurements are done. Were 1+ month out which means shit tons of shekel seeking faggots will be dumping nonsense misinformation until they get their shekel release
> It's possible with 4000Mhz ram
As opposed to 3466 that I already run at low latency (3600 CL16 ram).. no it isn't possible which is why I'm calling bullshit.

No wonder it needs active cooling. Shoulda gone with 7nm

Do you want my dick size too? faggot

Like in dirt 4? BTW pic related is zen+, NOT zen 2 fyi.

GET FUCKED INTARD

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4.2GHz vs 5GHz LOL

You have no idea what you're talking about, which is the source of your problem. I will state this again. Physical wire length is the least important part of the equation.
Zen1 had high DRAM latency because the memory controller was sub par.
Zen2 has a different IMC. That alone accounts for the decrease in access latency. The increased wire length from having two chiplets does not matter.

Back in the late 2000s intel released some Core2Extreme chips which had an external chipset memory controller, and they ended up having lower latency than competing AMD chips with integrated controllers.
The controller is everything. Wire length isn't.
anandtech.com/show/2050/3

Try actually learning something instead of spewing buzzwords you don't understand, dipshit.

Where the fuck did you get this?

>watermark clearly visible
>asks for sauce anyway
A /gif/ regular I see.

One good and informative post every 20 shit ones, nice

> You have no idea what you're talking about, which is the source of your problem.
I'll remember that when I reflect on my graduate degree in comp eng. and my ongoing work in the industry.
> I will state this again. Physical wire length is the least important part of the equation.
I will state what I said again : I'm speaking about pipeline features and clock domains. Something you obviously have no understanding of because you keep screeching about wire length and subsequent signal propagation as if were in intro to ECE 101.
> Zen1 had high DRAM latency because the memory controller was sub par.
Understood faggot
> Zen2 has a different IMC
Understood faggot
> That alone accounts for the decrease in access latency.
It doesn't because a relative latency figure is present on 2700x if you're willing to shell out $1,000 for a stick of ram. See pic fag.
> The increased wire length from having two chiplets does not matter.
I was speaking about : clock domains + pipeline features not wire length newfag
> Try actually learning something instead of spewing buzzwords you don't understand, dipshit.
Try getting a degree in comp eng. so you dont sound like a retard who keeps railing on and on about signal propagation (the least factor in all of this) which is not what I was referring to.

So, as I originally stated, these numbers are horseshit as it's likely being done on an unreasonable system, conditions, or a software bug. Disinformation for shekel clicks as we are a month out from official info.

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A shit tier post that is summarized as :
> Signal propagation isn't significant
DUH
> Informative post
Because you're a brainlet w/ no formal education

It honestly would not have helped much
The chipset woes stem from PCIe 4 requirements which require alot of redrivers to keep up signal integrity

honestly at least for gaming amd is just too expensive. rather get a good intel and enjoy good high framerate gaming instead of destroying your wallet with amd

>good intel
Doesn't exist. They're all pozzed.

>comp eng.
Too dumb to cut it in EE?

>the retard who knows literally nothing about analog or digital signaling now attempts to spew more buzzwords
You're not fooling anyone, nor are you going to earn any ecred by making up bullshit on an anonymous imageboard. Passive elements in the signaling path aren't adding any significant latency. Ever. No amount of sperg posting will ever change this. If they were increasing latency to any real degree they'd be degrading the signal. Its not happening.
The memory controller is the only thing that matters here. As already shown, DRAM access times of various CPUs can have an incredibly wide gamut of figures depending entirely on the controller and nothing else. There isn't anything even remotely questionable about DRAM latency dropping from the range of 90-80ns to 40ns with a new generation of chips.

Go join the OC3D forums if you want to lie and impress retards. No one cares.

More like a 1st year CS drop out who can't read a Fudzilla article without looking up words on wikipedia.

we NEVER saw the actual cpu being clocked if it was delided or not

this is just intel saying bullshit to customers

> Too dumb to cut it in EE?
Too smart to specialize in chinked (exported) EE.
I have a dual degree in EE and CE btw. Not that it matters. CE btw is how chips are designed not EE. The EE work is done closer to manuf in chinkland where all of the manuf plants are.
> tfw butthurt EE fag exposes himself

> You're not fooling anyone, nor are you going to earn any ecred by making up bullshit on an anonymous imageboard.
Come again EE fag?
en.wikichip.org/wiki/amd/microarchitectures/zen#Clock_domains
Now where do you think this new I/O chiplet fits in and how is it interfaced to the CPU complex? with an additional clock domain. Clearly, you are a complete EE fag w/ no understanding of CE.
> Passive elements in the signaling path aren't adding any significant latency.
Lets see if the retard spotted the bandwidth variations in L1/L2/L3 in 2700x vs OP and understands why this shifting occurs alongside w/ a latency drop and what that will do to real-world performance/latency.. Lets see if the EE fag can transition to CE.
> Go join the OC3D forums if you want to lie and impress retards. No one cares.
Take your sperg-lord rants over to EE-times.
>More like a 1st year CS drop out who can't read a Fudzilla article without looking up words on wikipedia.
Spoken like a true EE fag w/ no understanding of CE/Cache hierarchies and latency fudging that has negative implication for cache hierarchy performance and real world performance

>I have a dual degree in EE and CE btw. Not that it matters.
lol you are so full of shit.

Leave him alone. Hes already sperging out in another thread, and I can only imagine it took him a lot of hard work to google all those buzzwords.
His tender ego can't handle any more bullying.

> Your post shit all over me and my lack of understanding of CE/Cache hierarchies and memory controller architecture that this is my reply
I know user.. I deal w/ EE fags like you all the time. Pro-tip for this discussion, take OPs pic and put it next to and explain to me why L2/L3 bandwidth is in some cases 2x higher in the 2nd gen than it is in 3rd gen and what this has to do w/ the latency drop. Lastly, how this will results in negatively impacting certain data flows whereby 2nd gen will be faster than 3rd gen. Show me the power of your EE degree that wasn't coupled with CE physical layer fag.

I thought you said price didn't matter.

> cope
flattering

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Not that guy but this is (You) rn
Jow Forumsamd seems more like your speed

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>samefaggin this hard
It's ok user. No one is judging you for dropping out of college. Your 9900K was totally worth your mom's money.

>it has to hit two chiplets vs one?
Memory controller is in io die.

>$
last non-goof CPU from AMD was the ryzen 1700
it's been downhill since then

>make unsubstantiated claims
>recoil when people ask for evidence
Have a (((you)))

With amd I still somehow expect to plug my midi controller into the machine and then somehow get like 10ms extra latency. Then I'd ask online about it and amd shills would be like, "ACKSHUALLY, THE AMD PROVIDES SUPERIOR LATENCY ACCORDING TO (benchmark), STOP BEING AN INTEL SHILL."

Show me any real world examples of amd being superior and then collect your shadenfreude at the expense of the intel fanboys.

Actually, fuck you all you are /v/ transplants hat late about technology when 95% of the time you just mean video games.

Where's L1? Where's L2/L3?
How does data flow? What checks are made and have to be synchronized in the cache hierarchy? How is the performance dependent on size/location?
Claim is substantiated by bandwidth being lobotomized In L2/L3 in 3rd gen.. Something that any person with a sound understanding would look at first before running their mouth. Meanwhile you're sperging out about physical signal propagation as if you're talking to a pleb on the street. Seems you're the one who got caught bullshitting. The data/performance information speeks for itself. You're just too dumb understand it after all of your cope posts.. Again, explain the performance being halved in L2/L3... I'll wait on your superior input

I am already seeing the issue w/ the huge drop in L2/L3 bandwidth. It's dam near cut in half from 2nd gen to 3rd. I'm still waiting on this spaz-lord EE fag to recognize it as he tries to cope post along w/ his fanbase of brainlets.

>going to such lengths in pure blind sperg rage to try and save face
You're right, genius. The DRAM access times of the memory controller can literally never improve. Ever. Whatever helps you sleep at night, NEET.

the reports are 18% ipc... and 20% lower clocks, coupled with fewer cores and shit yields.
10nm is a mess and intels hope is getting their next node running

i don't really understand what motherboards have to do with RAM clock compatibility.
Isn't RAM hooked up to the CPU? Does it go through the chipset first?!

Why would they wait to 2020 when they can get EPYC or TR NOW?

Didn't even bother with the 16c Zen2.

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>has not heard of intel swiss cheese technology
Have you been living under a rock these past 18 months?

> has no answers.
> I've won
OK
> The DRAM access times of the memory controller can literally never improve.
Yeah if you fuck the cache hierarchy dynamics which is reflected in the screencaps and data (point was proven). Again, you're just too dumb to realize it.. That or, as I stated, you're an EE fag who has no understanding on how cache hierarchies work and what impact it has on latency and what occurs when you put L3 off chip and it has to cross multiple clock domains. There's an easy way to deal w/ a faggot who attempts to punch above their weight.. I put the data right in front of you and you're still unable to understand the implications. You've been outtting yourself in every boneheaded reply. Stick to the physical layer EE fag.. Stop trying to larp as someone who understands CE. Oh and tell your chink co-workers I said hi because that's about the only people left in EE.