C-chiplets are totally not going to degrade latency

You have no understanding on the topic but whatever floats your boat.
>victim cache making up for mamory latency
lel

Lmao and the i9 is still worse

DDR4-5133 sounds like a premature sign of DDR5 arriving

That's what I said this entire time. They absolutely need the larger cache to compensate for greater memory latency, and that's why they only mentioned "lower latency" in close conjunction with "twice the cache".

Hint: Not everything fits in the cache.

>That's due to die to die comms.
Of course. That's exactly the point.
>The latency issue is gone and Zen2 likely has better latency than even intel now. Cope harder
Wat. Did you even see the image?
>9900K: 43 ns
>Ryzen 3: 67 ns AT BEST

wait so the benchmarks were run with 5133Mhz ram and intel still won? kek

it looks like it still somehow performs in vidya if that's what you're worried about

I wasn't. I was just annoyed by all the idiots constantly spouting that chiplet design isn't going to affect latency.

Which mem speeds are those cpus on your graph running? Or did Intel Corporation (((forgot))) to include that info when they handed you that copy to make the thread?

still worse than meshshit

Attached: Intel-AMD-Naples-Reply-13-1080.348625475[1].png (1500x844, 210K)

Not sure, it was just a Google Image result. I'm sure you can find your own such results.

Either way, the point wasn't to compare with Intel, but with Zen 1.

so don't go over 3200 is what this graph says?

3200CL14 is B-die territory and I'm assuming 3600CL16 would be similar. All else equal, 3600MHz will offer more bandwidth

You're correct. Can't argue against this. It's looking bad. However, for real-world performance the L3's huge size hides this and it results in higher IPC for single/multi-threaded than even intel. All architectures have tradeoffs. The important thing is to balance it in real world performance. Depends on the workflow simply. For me, I do a lot of random access, so I take a hit. However, I am aware of this and adjust accordingly. The price/value is what sells me tbqh.

Both of those are B-die spec.
Straight 14's @3200 or straight 16's @3600
Glad I have some from the over-priced era in the prior year. That being said, i'm sure it will run bargain bin timings too now that its decoupled from infinity fabric to a degree.

The graph says its the sweet spot which any seasoned builder knows. Insane ram clocks are a meme because the timings increase and it negates the over-all performance. Thus the sweet spot for which you get great clocks/timings is 3200@cl14 and 3600@cl16 ... I have both kits running in my current setups. So, i'm good

>LATENCY IS HUGE
>What does it actually matter?
>IIITTTSS HUUUUUGGGGEEEE!!!!

Memory latency is most likely The Main Reason why Zen 1 loses to Intel. The vast majority of non-HPC software does pointer chasing somewhere.

The performance problem with increased memory speed here is more lagging uncore speed than timings.

Attached: TravisK_DonW-Next_Horizon_Gaming-Ryzen_Deep_Dive_06092019-page-017.jpg (2000x1125, 207K)

It matters for everything that hits the ram constantly. Like games and anything that requires consistent user input.

so basically, what you're telling us if if the latency was in Zen1 levels, intel would be fucked in the ass?

They included benches of software that normies and plebs use. No such software does tons of random access outside of cache lines especially with an L3 that big. So, the memory latency is effectively hidden. For serious compute, this is an issue but is also mitigated using clever micro-architectural features. I think its great that they're exposing details about the micro-architecture to wider audiences but it also results in forum faggots behaving like they have a PhD in compute architecture with years of industry experience.. The only thing that matters is real world performance. Less than 1% of the population is equipped to intelligently comment on micro-architectural specs in a vacuum.

What I stated is CPU agnostic. As clocks rise, so do timings. There's a sweet spot and then there's idiocy on either side which is what the graph clearly depicts. This holds for intel too. There has to be a sync between the Ram clock domain and the CPU, at such a point you either do full coupling (zen v1/v2) or you do ratio Zen2 which is what intel does which is why clock scaling is shit for ram and barely changes performance. So now, fags can shill just like incel fanboys about their insanely clocked ram .. meanwhile, under the hood, it doesn't change performance much and makes it worse even in some cases. Glad I understood this and loaded up on 3200CL14 b-die and 3600CL16 b-die. Going to do my kike ripper build tonight now that I got price confirms from Zen2. Seems I will hold out until there are significant price drops. I'm done for 5-10 years being an early adopter.

Yes but that is impossible with chiplets, increased clock domains, a huge L3 that adds latency, and a new chip in between the ccx and ram which is fine. THe end state performance is what matters and Zen2 outperforms intel in everything. Latency matters and then there's 100s of other micro-architectural features that make it unimportant for the majority of work flows.
Games don't do random access.. They design them to do memory access along cache lines which masks latency and they pre-fetch to hide mem latency... modern CPUs even do this on their own... Watching youtube videos/reading anandtech doesn't educate you on the idiosyncrasies of CPU architecture.

>No such software does tons of random access outside of cache lines especially with an L3 that big. So, the memory latency is effectively hidden. For serious compute, this is an issue but is also mitigated using clever micro-architectural features.
You have it the wrong way around. "Heavy compute" is usually far more regular in its memory accesses and also has more independence between its accesses, whereas "ordinary software" tends to do more pointer chasing, which is where memory latency really matters.
>Less than 1% of the population is equipped to intelligently comment on micro-architectural specs in a vacuum.
I can at least comment on the patterns I've observed in my own software. Profiling it, it very much tends to be bound on dependent loads.

>but it also results in forum faggots behaving like they have a PhD in compute architecture with years of industry experience
Such as yourself?

>recommended price/perf config: 3600 cl16
>$150
christ, that's almost double what a typical 3200 cl16 ram costs. That being said if they used the 5133 on the benchmarks which they probably did then amd is trully finished

If you don't have at least a bachelors degree of study in both comp sci/comp eng. please kindly stfu :
> en.wikipedia.org/wiki/Cache_prefetching
> gamedev.net/articles/programming/general-and-gameplay-programming/cache-and-how-to-work-for-it-r4020/

> A wide range of applications — from games to database
management systems — are based on dynamic data structures linked together via pointers. However, such accesses
are often not governed by the localities exploited by traditional cache organizations. Furthermore, misses to such
pointer-based loads, especially recurrent load accesses, significantly restrict parallelism and expose the full latency to
memory.
In this paper we propose using a Pointer Cache to accelerate processing of pointer-based loads. The pointer cache
provides a prediction of the object address pointed to by a
particular pointer. If the load misses in cache, consumers
of this load can issue using this predicted address from the
pointer cache, even though the load itself is still outstanding.
Using the pointer cache for just value prediction provided
a 50% speedup over stride prefetching for a single-threaded
processor.
> I can at least comment on the patterns I've observed in my own software.
aka you have no clue wtf you're doing or how to write advanced software.
I have a masters and 7+ years of experience.
Enough to know my limits and not over-state my understanding of something unlike a forum faggot who has it all figured out. Like this faggot :
who doesn't know how to write cache optimal software

There's shitty ram at this spec. 16-18-18 not 16-16-16-x. Ram prices have plumeted 50% from a year ago. Only a spec faggot is going to run at 5133 as that is worse performance than even 3200@CL14. AMD isn't finished... their CPUs will now run the same shitty ram intel's CPUs can which have no performance impact as you scale beyond 3200/3600 as well.

>If you don't have at least a bachelors degree of study in both comp sci/comp eng. please kindly stfu :
So do I, as well as 15 years of professional programming experience.
>all pointer chasing can be eliminated, just follow this simple guide where we describe what cache is
Your deep experience really showing off.

>So do I, as well as 15 years of professional programming experience.
So do I, as well as 999999 years of professional programming experience.

SEE I CAN DO IT TOO, INTURD.

>who doesn't know how to write cache optimal software
Also, it's not just about "my software". Do you really think 99% of software isn't poorly optimized?

>5133 as that is worse performance than even 3200@CL14
They obviously had it tweeked. I'm pretty sure they weren't trying to sabotage themselves when they demonstrated the cpus with such RAM.

Yet you don't know how to write cache friendly hardware? Wtf do you code at the web layer nigger? I can find juniors at University who know how to write cache friendly code. Games and game engines don't do pointer chasing faggot. That was the red-flag right there. Some of the most optimized code centers on games that page in scenes and relevant data structures in blocks .. It slams the cache continuously. This is basic shit anyone knows so your experience means fuck all apparently because you're still trying to argue an invalid point.
wtf does someone shitty software have to do with an optimized micro architecture and modern cache design? Write better software and you get better performance. I'm not going to jack off to incel while ignoring how shitty some code is
Of course it's tweeked.. Only retards clock their ram that high.