PCIe 6.0 Announced, Spec to Land in 2021

Right in time for DDR5 & Zen 4

>Just wait user

anandtech.com/show/14559/pci-express-bandwidth-to-be-doubled-again-pcie-60-announced-spec-to-land-in-2021

Attached: PCI-SIG DevCon 2019_Briefing Presentation_final_06.png (1920x1080, 299K)

You're not getting PCIE6 on consumer boards before 2014, materials are too expensive that low end boards would cost close to $300

2024*

>from the post:

[As for end users and general availability of PCIe 6.0 products, while the PCI-SIG officially defers to the hardware vendors here, the launch cycles of PCIe 4.0 and 5.0 have been very similar, so PCIe 6.0 will likely follow in those same footsteps. 4.0, which was finalized in 2017, is just now showing up in mass market hardware in 2019, and meanwhile Intel has already committed to PCIe 5.0-capable CPUs in 2021. So we may see PCIe 6.0 hardware as soon as 2023, assuming development stays on track and hardware vendors move just as quickly to implement it as they have on earlier standards. Though for client/consumer use, it bears pointing out that with the rapid development pace for PCIe – and the higher costs that PAM4 will incur – just because the PCI-SIG develops 6.0 it doesn't mean it will show up in client decides any time soon; economics and bandwidth needs will drive that decision.]

Yes, that's what I said.

Not likely.

And the author appears to ignore the "minor" detail of PCIe 3: Announced in 2007 and avaiable in consumer products in 2010. It took 9 years before PCie 4. Not two, not four, nine.

PCIe was announced in 2011, btw. Didn't arrive in 2013 or 2014 or 2015. It's coming to consumer products this year.

None of these matter, this is 2019, not 2007 and as you can see we're in rapid development pace unlike of what happened in the past. furthermore you're missing the fact that many manufacturers start developing/releasing their boards in a early draft stage.

>Draft process

There are 5 primary releases/checkpoints in a PCI-SIG specification:[69]

Draft 0.3 (Concept): this release may have few details, but outlines the general approach and goals.
Draft 0.5 (First draft): this release has a complete set of architectural requirements and must fully address the goals set out in the 0.3 draft.
Draft 0.7 (Complete draft): this release must have a complete set of functional requirements and methods defined, and no new functionality may be added to the specification after this release. Before the release of this draft, electrical specifications must have been validated via test silicon.
Draft 0.9 (Final draft): this release allows PCI-SIG member companies to perform an internal review for intellectual property, and no functional changes are permitted after this draft.
1.0 (Final release): this is the final and definitive specification, and any changes or enhancements will be through Errata documentation and Engineering Change Notices (ECNs) respectively.

Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources.

A PCIe spec a year keeps the goyim in fear!

Just because you recently purchased a low-end PCIe 3.0 mb this doesn't mean that progress must stop, All these naysayers are usually some poorfags with no intention to buy anything for the next 10 years.

So more Bandwidth and more Latency as well? Why would anyone care?