Since the CCX'es are on the same die whats even the point of them? Seems like its just unecessarily introducing complications and added latency. A similar design to Intel where the cores communicate through the shared L3 cache would have been much better, so would even Ringbus for up to 8 cores.
I get the chiplets since they are different dies and increase yields, but the CCX design seems completely unnecessary.
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Good yields. Monolithic garbage is dead.
I addressed this in the post, its on the same die so it does nothing for yields
Because the CCX layout is a known entity from Zen and Zen+
When moving to 7nm, you don't want to drastically alter EVERYTHING especially when you don't know how that will effect the final silicon.
Because the ringbus is only substantially lower latency than the inter CCX lines for the nearest cores. It's a different solution to the same problem of inter core data path bloat. They did choose to attack the problem more aggressively than Intel to push density higher. IMO it's a good tradeoff because the extra area can be dumped into more L3 instead but I'm not an engineer so who knows.
I'll add some more. The lowest latency highest bandwidth solution would be to have every core directly connected to every other core. That would be a massive waste of die area at high core counts so some compromise is needed. Trade inter core data paths for die area to use on other things. The ringbus is one compromise, the skylake-x mesh is another, the infinity fabric is another.
>every core directly connected to every other core
Is that even possible past 2 cores?
I coudnt find a number for the ringbus latency but up to 8 cores i have a hard time believing its anywhere near cross CCX latency, which is afaik 120 ms for Ryzen 1 and i dont think it has changed for Ryzen 3. For comparison the latency within a CCX is 40ms, i cant imagine Ring being higher than like 60 at the highest point at or below 8 cores.
You can keep increasing the core counts without having to worry about yields
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Because it's meant to be something you buy if you can't afford Intel.
Imagine how poor Google Amazon and Microsoft must be if they're switching to Epyc.
Zen has lower latency core to core inside of the CCX than intel does with their ring bus or ring mesh. A pretty damn big benefit to the arch. They're pretty tightly integrated, however signal routing is the most complex part of IC design. The dies are broken up into these groups for the sake of simplicity.
Hello, don't listen to all of these faggots OP, im here to give you the real informed answer.
Firstly the anons who said it's because of segmentation arent wrong but that doesn't answer your question why they still do it for zen 2. Pic related is a zen 2 chiplet and the dual ccx's are in the same configuration as zen 1 just beside one another instead of being placed across.
Simply put, they use the ccx design with zen 2 because its cheaper to keep the cores mostly the same, than it is to spend tons of money developing a new core from scratch. There is absolutely no real reason to use the ccx design over ringbus other than its cheap and already designed and implemented. And they already have full if scalability implemented so a lot of work is already done for them.
At computex lisa su said they were going after low hanging fruit and latency with the zen design as it goes on. Im betting as time moves forward the ccx is going to see some massive changes for the sake of IO and reducing latency, and will effectively cease existing in their current form
Its on the same die though
So? Just make low binned chips.
Inter-CCX latencies are lower than Intel
Why do you think mainstream Ryzens are 6 core instead of 8?
Imagine having to make shit up because you've got nothing else going on
Denial is the first step
Scaling cores inside a CCX (Every core is directly connected to every other) becomes increasingly difficult past 4, because adding one core means you have to fit it and route new buses for it to every core. That's why Intel uses Bingbus/Mesh, this is just AMD's solution to the same issue.
You are an idiot.
CCX design lets them more easily disable large chunks of the die without affecting the rest of the CPU. It SUBSTANTIALLY increases the amount of useable dies.
>Phenom II x2/x3
>4/6 core FX
Binning/die recycling isn't special to zen
Not really. They just disable 2 cores and bin it as as a lower spec CPU. Same thing that both Intel and AMD have been doing for years
You can do that regardless of CCX.
But you can't just shove more of them and create behemoths like Threadripper with the same dies.
You are either smarter than every single AMD engineer or just dumb as half this board, and I think we already know the answer.
Latency inside CCX is LOWER than ringbus,
It decreases memory latency within the CCX itself due to lower distance between the cores to the cache.
Ringbus starts really falling off after 8-10 cores, and also consumes a ton of power.
With the CCX design, each core has a direct connection to the cache sections.
Even zen1 had lower intra-CCX latency than Intel core architecture did.
It also fascilitates wiring to the cores to cache outside of the CCX.
I was saying for a long time that, no, Zen2 is likely not going to be more than 4 cores per CCX and will likely stay 2 CCX per die because of how more cores per CCX would fundamentally and negatively change the cache layout.
You can see in the way the cache is broken up into 4 L3 segments. Each core is wired to all 4 of them. If it was 8 cores per CCX, there would be a lot more wires to wire each core to 8 L3 segments instead of 4. Instead of 4*4+4*4 it's 8*8. So that's another reason, other than how it'd slow down intra-core latency.
You are not getting the point, they are using the same dies for virtually their whole lineup, that's where the increased yields come from.
But all their dies are 8 core dies, its not like they are producing dies with more than 2 CCX'es anyways that they could benefit from any possible increase in yields CCX'es would provide. They just take multiple 8 core dies and put them on one chip to make high core count CPUs, so why not make those dies monolithic instead of unecessarily dividing them into two.
Why are you guys all NEET losers if you have all the answers that a multi-billion dollar corporation doesn't? Really makes me think.
>so why not make those dies monolithic instead of unecessarily dividing them into two.
There are hundreds of considerations for die layout. To assume that the CCX arrangement is "unnecessary" just makes you sound like a retard. Signal routing, thermals, mitigating some potential defects by not consolidating all of your dense logic in a single area, etc.
Making an 8 core CCX vs the current existing quad core structure would require drastically more data fabric, more associativity in the caches. Nothing is as rudimentary as you seem to think it is. Believe it or not people who design ICs for a living actually know more than you do.
Ask the genius OP that can't use google and find his answer in 10 seconds instead of thinking he's smarter than literally thousands of engineers.
Im not saying there is no point to the CCX design, im just saying yields are not the reason.
>ms
You're off by a few orders of magnitude
>its on the same die so it does nothing for yields
this is where you're wrong dumbass
Source?
because they're poor and copy-pasting them is essentially free
It would require exactly the same amount of IO other than cache links (which is essentially the only limitation of IF. You can already consider them as 8 core ccx chiplets, the difference between each ccx is minimal, and AMD isn't even binning them into quad cores like they did zepplin dies because yeilds are so good.
Lol
So thats why they are so cheap
These right here are what you call niggers, folks.
Hit a nerve, huh