MAINSTREAM AND HEDT ZEN 2 CONFIRMED TO HAVE 8 CORES PER CCX, 16 CORES ON AM4 POSSIBLE NOW!

i don't believe you

Says right in the picture: that's its an ENG SAMPLE. Dipshit.

If AMD can get Zen2 ROME to clock up to 2.35GHz stable, we're looking at FP32 performance of 779.49GFLOPs & 641.02GFLOPs in FP64 performance in a 64c/128t system. If we double that for a 2U system, we're looking at 1.5TFLOPs FP32 and 1.28TFLOPs FP64 performance on a fucking CPU.

i don't believe that it will hit 2350 mhz on air with all cores active

wccftech.com/amd-epyc-rome-64-core-7nm-flagship-cpu-clocks-2-35-ghz

And that's just preliminary tests with engineering samples. They actually believe they'll be able to achieve stable 2.8GHz at the very least on all 64 cores with water, with maybe even getting into a 3GHz territory on best bins.

This will be extremely interesting to see as the zen+ 2990WX can crank all the cores to 3.4GHz and only use ~6W/core. If AMD can cut it down to ~3W/core just by cranking the frequency down to just 2.4 GHz intel is going to come unglued.

Attached: 2990WX POVPower.png (2127x729, 139K)

>At the current time being, the most powerful Super Computer in the world (#1 in "TOP 500") is IBM's Summit, which uses 9216 22-core/176-thread (IBM does 8 threads per core) POWER9 processors. Summit's documented throughput is 122 Petaflops (1 Petaflop = 1000 Teraflops).

>Currently, the Super Computing system which used the most individual CPUs in it's stack, was IBM's "Sequoia", with it's 98304 CPUs, all of which are 16-core A2s.
>But Sequoia is not even in the Top 5 of the "TOP 500" right now. By sheer performance alone, Chinese Tianhe-2 sits at the 4-th place, and that one uses 32000 12-core Xeon E5-2692 processors, which resulted in roughly 34 Petaflops of documented performance.

>Now, then...just a couple days ago, Stuttgart's (Germany) High-Performance Computing Center (HLRS) announced that it's preparing to build a "HAWK" general purpose (aimed at open public usage) Super Computer with 10000 of 64-core/128-thread Zen 2 EPYC-based processors, which will result in exactly 24 Petaflops of documented throughput. The HAWK is going to be fully operational and available to the audience at the Q2 of 2019.

>Let's see now: 10000 64-core Zen 2 EPYC processors result in exactly 24 Petaflops of performance.
>Meaning that a 20000-CPU system would approximately net 48 Petaflops, whereas 40000 CPUs will be 96 Petaflops respectively.
IBM built a 98304-CPU Super Computer in the past, meaning there's nothing that can stop someone from building a, let's say, 80000 CPU-based Super Computer on Zen 2 platform, now. 80000 Zen 2 CPUs will result in 192 Petaflops of performance (70 Petaflops more/faster than current #1 in world's TOP 500). Now take into the consideration that Zen 2 is much more efficient (the friggin' thing CAN run on AIR), that Zen 2 supports much more RAM than Xeon, that Zen 2 is MUCH cheaper than either Xeon or IBM's POWER, that it's much easier to build/expand/maintain, and also that it's WAAAY more secure than both Intel and IBM combined altogether.

Rome is already racking HPC wins during fucking validation.
Intel is in deep, very deep shit.

The EPYC 7601 has an all-core turbo of 2.7GHz and a TDP of 180W. It runs on air. The 7nm node has at least a 50% power reduction. So double the cores would take about the same amount of power. AND you're talking about even lower clockspeed, which probably isn't even actually limited by power, but other physical constraints like capacitance between traces, etc.

This. AMD did not have even one preannounced design win before Milan, 1st gen Epyc. All the announcements were all about validation and testing, which means the big companies paid nothing but time and AMD provided all the equipment and money to give it to them to start using it, which only happened during this year. Having Rome coming out strong means there is going to be major market erosion from Intel. It's not going to be a flip of 2-3%% to 98% of server market but more like probably more like 25% 75% best case scenario. So Intel will take a hit but they definitely deserved this rude awakening after stalling for almost a decade.

im not an engineer and i have a 2600, if one were to double the amount of cores on an am4 chip, wouldnt we get a very large concentration of heat? would we be looking at intel levels of temperature?

>>Intel clocks drop to 2.1ghz on their 28 core chip
>only first 2~4 cores get 2.1, everything else gets downclocked to shit
>Zen sustains stable clocks on all cores at all times

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It's not that simple, see 2990WX witchcraft

Unlike Intel, AMD actually managed to get a proper node shrink this product cycle.

>wouldnt we get a very large concentration of heat?
Zen operates at two modes: either 1x25 PPC/IPC per same TDP/thermal envelope as Zen+ (which is already a big update from gen1 Zen), OR Zen+ tier performance at...0.5/half of Zen+'s TDP and thermal envelope. Regardless of cores and threads.

Sweet, I just want a 8 core 1CCX chip that clocks to 5ghz so I can play CSGO and do some shit on the side

Even based Emelianenko approves of Zen 2 over dying Intel platform

Are we talking about a weird near future where you can have a consumer grade, 8 core laptop?

>So Intel will take a hit but they definitely deserved this rude awakening after stalling for almost a decade.
Less stalling and more lack of any long-term vision.

You won't need 5GHz and CSGO uses like 2 threads max. Even a 10% IPC boost means 4.0 GHz zen 2 = 4.6 GHz coffinlake before any higher clocks are applied.

This "future" is LITERALLY a couple months away, matey. Fucking WEEEEEEEEEEEEW.

Zen2 APUs are a while away.

>Zen 2 operates at two modes
fixed

We already have that: asus.com/us/Laptops/ROG-Strix-GL702ZC/

If AMD can't cram a zen 2 threadripper in a laptop I'm going to be mad.

The main story in Zen2 is not core count in vaccum, but overall system/socket perf.

if am4 can achieve 16 cores would you even need a threadripper workstation

That's a high end laptop, i'm talking about normietops making 8core configs so common, developers have no choice but to take advantage of it.

Memory and I/O.

Well for stable 240hz/fps every extra mhz matters honestly. But hopefully you're right.

And I know 8 cores is overkill for CS, but it will be really cool for some other stuff (rendering, VMs, and even streaming when my friends wanna watch me play kek).

Still no later than Q2 2019, which is summer, which is just a couple months away for me personally. I'm used to WAITING for the FINE WINE to MATURE well enough it becomes GODLIKE.

Attached: GIMPWORSE VS FINEWINE.png (736x736, 1.55M)

The APUs are Q4 2019.
AMD is mobile last, and Rome goes to hyperscale somewhere Q2 2019.

>would you even need a threadripper workstation
THREADRIPPER 2 will have 32+ cores at mid and 48/64 at top, so it's obviously still a HEDT upgrade if you're a serious powerusing faggot.

AMD should be able to do 8 cores inside 30W, so there's potential for it. The problem is that I'm not sure it makes sense as far as sales go; I don't think they'd sell enough of those SKUs to justify their existence.

But I do think AMD's parts on this new node are going to shit in the mouth of every low power part Intel has to offer until 10nm is actually working. Which is nice, since I really like laptops without fans.

AMD can already do 8c in 35W.
Just with ~2GHz clocks.

i really hate my laptop 7700hq hitting 93 on an undervolt, so hopefully they stick zen2 in a laptop.

The other issue to note is that the Power9 uArch that's in the Summit Super Computer, completely disregards power/heat for raw performance. Which is why it only needs 9,216 22c/176t config CPUs together for 122 PFLOPs.

Power9 die: nextplatform.com/2016/08/24/big-blue-aims-sky-power9/ | ITS FRIGGIN' HUGE. We're talking nearly on par with Skylake-AP packages. With that kind of power and industrial grade cooling on tap, it's no surprise that IBM is taking the top. But if we have to factor in efficiency, power/heat AND performance all as integral categories to success, then IBM's Power9 is an extremely limited scope usecase. Skylake-AP is much broader than the Power9, but still fails with regards to perf/watt & heat compared to Zen2 EYPC. Which, ironically, Summits both IBM & Intel's high core/thread offerings while massively using less power and generating less heat.

AMD kept winning hyperscalar and HPC wins during validation as this guy said here: , all because of the raw efficiencies of Zen2. Further, we're still on pure 7nm. End of next year, we'll see 7nm EUV, which will bring with it a reduction in area per design print by 15-20%. Even if we assume the conservative estimate of 15%, that means that transistor density will further increase to allow for Zen2 EYPCs to be able to hit 2.5GHz all core base clocks from 2.35GHz expected (current) targets.

Currently, Zen1 EYPC 7601: amd.com/en/products/cpu/amd-epyc-7601 | can do an all core boost to 3.2GHz. It's base clock is 2.2GHz. If Zen2 brings a doubling of cores & threads with a .15GHz increase in baseclock performance and 7nm EUV adds another .15GHz baseclock increase. Then we can, assuming a linear scaling in performance (as noted by IF behavior), say that Zen2 EYPC 64c/128t can safely deliver a 3.5GHz all core boost clock.

In a 2U config, we'd be looking @ 128c/256t @ 3.5GHz (all core) for 360W combined TDP. Cascade-Lake AP is expected @ 48c/192t @ 2.5GHz for 250W.

It's possible though thermal constraints prevented the laptop I linked to from going above 3.2 GHz on all 8-core load but given the massive jump to zen 2 from zen 1 I could see some monster raven ridge chip going to at least 35W thin clients. Base will probably be like 2.4 GHz but I can see it having 3.6 GHz turbo for some cores and 3.2 GHz for all cores.

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They will stick Zen2 everywhere.
Rome is 250W, not 180W for top roadmap bin.

If AMD went that route it would require a new socket I think, since Threadripper is rated for like 180W and I can't imagine Zen 2 being so much more efficient they can fit 16 cores in 95W with AM4. It's possible they could create a new socket keying that is compatible with AM4 chips though.

>AMD can already do 8c in 35W
It's two CCX, which sucks ass, though.
Now we can have 8 cores on a single fucking CCX chip, which means PERFECT-FUCKING-LATENCY and that in itself leads to SUPER-efficient and VERY great performance in gaymen, productivity, serious works and other shit. PURR-FECT for notebooks if top Zen 2 APU is going to have a 1-CCX 8 core option. And that's while having great clocks WITH low power consumption. Just cannot fucking wait.

The entire AM4/SP3/SP3r2 infrastructure won't change until Zen4.

>It's two CCX, which sucks ass, though.
It doesn't.
>Now we can have 8 cores on a single fucking CCX chip, which means PERFECT-FUCKING-LATENCY and that in itself leads to SUPER-efficient and VERY great performance in gaymen
Cache latencies are already good, making them worse by complicating the interconnect is dumb.

>Rome is 250W
Wasn't that 2S? One should be lower.

that would be very impressive

Or low clock 16c 95W zen 2 chips, IPC uplift means even a 3GHz chip will perform like a 3.4GHz zen+. Given how 2990WX already does 6W/core @ 3.4 GHz I don't see how zen 2 wouldn't be able to do this at least.

You're probably right but don't completely kill the hope since we went from 16 to 32 cores on threadripper jump.

If you can make 8-core on only one CCX and have the igpu on the other die (also serving as I/O and shit like a console), i bet you can make the thing very cheap.

>It doesn't
Latency, nigger. Ruins gaymen and general productivity, Might be tolerable in a desktop environment, but absolute no-no in a mobile system.

Even so, it is an annihilating difference in capability. Companies will have to decide:

64c/128t @ 3.5GHz all core boost @ 250W

or

48c/96t @ 3.2GHz few core boost @ 250W. On pure technical differentiation, AMD already wins here. The next item of determination is cost. 48c/96t Cannon-Lake AP is going to likely be around the 15-18,000 dollar price range (given that their 28c/48t 8180Ms cost around there). The 64c/128t Zen2 on the other hand is expected to be between 5-7,500 dollars. You're getting 25% more cores and threads that can consistently all clock higher than the competition at the same TDP. That's nothing short of impressive.

The only item that can be considered an issue, that most of the hypervisor stacks have been designed and optimized for Intel uArches for over a decade and migrating from Intel to AMD platforms can be viewed as a significant pain point. But if AMD has managed to resolve that with companies like Vmware and RedHat to address the Xen issues for hot migrations, then there's ZERO reason not to change.

Anyone who stays or continues forward, with all of the above accounted for, is either doing it because they're fanboying or there's a legitimate business case wherein they can't change over at all. The latter entities will end up becoming like 0.1% of the market, and its completely fine if they stay. As for the rest, they're fanboying and are thereby costing their parent company crazy amounts of money needlessly. Shame on them.

So that explains . The i5-8400 is operating with 2666MHz RAM but the 2600 is using 3200MHz I think.

No, that's the top roadmap bin for a single Rome CPU.
AMD will, of course, offer >300W off-roadmap SKUs for water/immersion systems, too.
They literally told you that ten times over.
Memory, not cache.
Zen gains plenty of gaming perf by tightening the memory timings.
Tone down the stupid.

>Cache latencies are already good
90~170 in Zen, 40~140 in Zen+.
While Inturd sustained 40~70 across the board.

Zen 2 promises twice faster than Zen+'s, so roughly 20~70.

Attached: latency-pingtimes.png (832x537, 59K)

That's EXACTLY what PS 5 is, lel.

>While Inturd sustained 40~70 across the board.
Theirs is unified, Zen's is not, it's 2*8MB per Zeppelin and should be counted as such.

>because they're fanboying
You meant to say "being bribed with gorrilion of backhanded shekels"

>The only item that can be considered an issue, that most of the hypervisor stacks have been designed and optimized for Intel uArches for over a decade and migrating from Intel to AMD platforms can be viewed as a significant pain point.
Literally everything works on Naples just fine.
It's even deployed in cloud.
Go try new EPYC-powered aws instances.

>tfw intel will start offering to pay their electricity bills to keep market share

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I'm waiting for them to release t3a instances, since my project's cost target is within the scope of those types. Right now, I only see the R5a and M5a ec2s. Sucks man. As soon as they certify them for us-east-1, I'm going to be shifting all our environments over. A 10% cost drop across ~200 servers is going to be pretty big.

And the funny part is that it would completely fucking crush the PS4 in terms of CPU power, and that would allow it to run much more games at 60 fps (not that the american game developers would aim at this target frame rate anyway, but the capability would be there).
But what is even more hilarious is that the shitty jaguar cores actually were capable of easily crushing the Cell processor due how it was just a shitty GPU pretending to be a CPU.

And Rome will bring even bigger, fatter TCO advantage.
70-100% per socket perf lead over Cascade, and probably some ungodly AVX2 crunching power, assuming they did what I think they did, i.e. 4*256b units.

Why would this mean that 16 cores is possible on AM4. Is there a direct relation between a CCX and pinnouts or is that only what was done for ZEN1.

CCX is just a macro-block of cores and cache.
You're thinking of actual full dies, being Zeppelin for Zen1 and CCD for Zen2.

>confirmed
Can you stop using words you don't know, fucktard?

Size of package can be same while making more cores on same CCX package. Where you've had 8 cores via two 4 core CCX on gen1 Zen, now you can have 8 cores with just one CCX chip, meaning if you put two CCX in there - you get 16 cores in same size as 8 core gen1 Zen was or 8 core Zen+ is right now. Same socket, same sized CPU, twice more cores, better TDP and power envelope, higher IPC and PPC/IPC. What not to love? Not only you'll get twice as more cores on mainstream socket, but also higher PPC/IPC and lower power consumption/thermal output. And yes, pin counts are exactly same since wiring will be exactly same (only Infinity Fabric's wiring gets improved/reworked to obtain better latency).

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>and I can't imagine Zen 2 being so much more efficient

>Compared to TSMC's 16nm FinFET Plus (16FF+) technology, TSMC's 7nm technology delivers around 35% speed gain at the same power, or around 65% power reduction at the same speed.

fuse.wikichip.org/news/1815/amd-discloses-initial-zen-2-details/

They did EXACTLY THAT.

Attached: zen_zen2_changes_initial_disclosure.png (1447x785, 163K)

Good golly that's gonna be really nice for SIMD crunching, basically width parity with SKL-SP sans AVX512 support.

holy fuck

Will the gap still close for single threaded performance or are we doing MOAR COREZ all over again but much better?

It's some more IPC and some more clocks.
And more cores, much more cores, since servers want exactly that.

This one is a bit of an complete incognito.
There are improvements to the IPC, there are improvements to the clock, but if it will match or surpass the intel stuff, it's to be seen.

It already did, see The only reason inhell is able to scrape by is because they're binning the ever living fuck out of their chips crucifying like 90% of them for those 4.5GHz+ clocks and even then it's single digit better performance. AMD decided to play the waiting game and finish intel off with higher than coffin lake IPC and slightly higher clocks with zen 2. Intel is going to lose to every market imaginable.

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I can't be the only one that thinks Lisa Su is kinda hot right?

AMD said Rome would be up to 64 cores, and there's 8 chiplets, which would be 8 cores per chiplet.
Does not compute. Maybe the new CCXs will be 8 cores now, but with just 1 CCX per die
I'm a bit skeptical, tbqh

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>Maybe the new CCXs will be 8 cores now, but with just 1 CCX per die
That's what they're doing, yes. The memory controller, IO, and CCX interconnects are on that large central die, now, so the chiplet dies cannot have more than one CCX anymore. At least not for the EPYC designs.

and start fapping

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>Will the gap close for single threaded performance
It already did, with 2600/X and 2700/X. Zen+ outperforms 7700K and matches 8700K in gaymen.

who wouldn't want to wreck this?

No, you're just being stupid.
CCD can have a pair of 4c CCX, xbars are cheap anyway.
>The memory controller, IO, and CCX interconnects are on that large central die
CCD still has a CCM and an IFOP.

forgot pic

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Nah, let's be honest here: intel still wins with higher clocks but just barely and the only thing that intel has to hold a candle to the 2700X is a 5GHz housefire most motherboards will throttle to 4GHz if you attempt to run all cores at 5 GHz.

I didn't elaborate enough, but I was trying to say that I'm a bit skeptical of Ryzen or anything for AM4 will have more than one 7nm chiplet. 8 cores for consumer is still pretty good. Granted, I have no idea if Ryzen is even going to use the same multiple dies for CCX and I/O or f that's going to stay an EBYN/Threadripper feature for now

One chiplet is one 8 core CCX now. No more 2+2/3+3/4+4 kiddie fuckery, we BIG BOI SERIOUS BUSINESS GAME NAO.

Intel, she's not into hot heads.

>Nah
Go and slit your wrists, you reality-denying fuckshit. Now. Right now.

They will reuse 8c chiplet literally everywhere, from top to bottom.
That's the entire point.
Sandra leak is 16*16MB so 4c CCX it is.

Su only rolls with people who glue stuff together.

Last AMD presentation claimed around 27% improvement in overall performance. That apparently accounts for the predicted increase for both IPC and clocks.
Seeing how some Ryzens are trading blows with their equivalent Intel counterpart, but at a lower price, Intel is in trouble unless they unfuck their 10nm in 6 months or less

One chiplet is only the half of the size of AM4 socket CPU package, so it only makes sense to make 16 core 2 CCX package now to fully fill the space. They're LITERALLY losing NOTHING from doing this, as it's exactly same space that just got vacant due to old less efficient CCX design being kicked the fuck out. They're just taking out old shit and substituting it with a much better newer one of exactly same physical size. It's LITERALLY like hot-swapping/changing older smaller sized HDDs/SSDs in a NAS array for much bigger capacity units. Form-factor is same, available space is much larger.

>16*16MB so 4c CCX
16x16 is 8 core per CCX, you dumb shit. It's literally in the OP post, you fucking imbecile. Go and read shit, moron.