AMD Rome has doubled the cache RAM

REEEEEE-fil

Even better I want to install something like Damn Small Linux onto a virtual drive on the cache and run it. Then use the Ram as storage. No Hard Drives. Ultimate Burner PC

>mfw it could possibly run without any RAM

>It has 256MB of cache
256MB of total L3 cache? What the actual fuck?

One of my home servers still has that much RAM.

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My first pc had 2MB of ram lol. I upgraded to 4MB to be able to run SimCity 2000

>cache lowers latency
no shit faggot
>256MB
holy fuck
1GB cache in next 2 years

3800X 4.0/4.8Ghz with 16 cores, where?
3700X 4.1/4.9Ghz with 12 cores where?

>3800X 4.0/4.8Ghz
Considering 64c eng sample rome runs at 1.4ghz, i doubt that 16core will be 4+ at stock. 3.3/4.0 at 95-105w more likely.

The 64C engineering sample has more uncore than Intel has silicon dedicated to cores and cache.
And that's an ES, a LP one.

>What the actual fuck?

Future's so bright i've gotta wear shades.

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>Even better I want to install something like Damn Small Linux onto a virtual drive on the cache and run it. Then use the Ram as storage. No Hard Drives. Ultimate Burner PC
So there would be literally no way for any data recovery whatsoever once the power is cut?

whats the point of having so much cache?

To store all of the instructions.

You're looking at very early ES or a low power

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how many are there?

Yeah, the user said burner PC, probably to do illegal shit on

Makes batch processing faster I think. Each job has to be queued and "wait its turn" basically. More cache means faster processing as jobs are able to wait less due to being stored on faster cache.

Wrong question. The question should be "at what point does does having loads of cache slow down data fetching?".

Femember as a rule the bigger your pool of memory the longer it takes to read. Its why Intel's L1 and L2 are stupidly fast - to keep the cores fed.

You don't need more than 4MiB of CPU cache. Prove me wrong.

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>You don't need more than 4MiB of CPU cache
Of what level?

you don't need more than 640k they said

>walk into an AMD shill thread LITERALLY using pajeet marketing sites
>the vast majority of posters don't understand what a cache is

As an actual pajeet that works as a cpu architect, this deeply poos my loo

>cache ram

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*crashes premiere*

my first PC had 64KB RAM

All the pro-AMD threads are AMD shill threads

Just poo in the loo Ranjeet

poo in joo shitkike

good luck finding software that actually scales to that many cores

Someone post benchmarks from phoronix

He means real benchmarks, like SuperPi, and Skyrim, and CunterStrike and Quake 2

lol

>SuperPi, and Skyrim, and CunterStrike and Quake 2

Hmm, one of these is not like the others.

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>256MB of total L3 cache? What the actual fuck?
as CanardPC predicted. guess no one's laughing now

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>256MB of cache
jesus

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benis :DDDD

kek

Intel on suicide watch

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Seems Canard and swedish haggis were both on the right track. While Charlie "fuck intel" Demerjian keeps his juicy info behind a paywall he is also claiming (and has done for a while) Rome is a xeon killer.

>256MB
lol ok, I run intel and it has 32gb of ram

I understand that you can't make processors even smaller because of moore's law but I will never understand why you can't just make processors bigger. Like make it 8nm but twice as big

256 > 32
retard

>I understand
>can't make processors even smaller because of moore's law
>moore's law
>Like make it 8nm but twice as big

You don't understand shit, dumbo

How the performance of transistors would be different if they were bigger?
This shit for example is definitely much bigger than a standard processor. Why won't they make something like this but for pcs

why L1-2 are so small?
explain it like you would to your father

Small is fast, big is slow.

Why link to a fennomongolian site?

>processors gonna have gigabyte size cache in your lifetime

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You're a big boy

Why is doubling something with a new version of a server cpu surprising?
I thought its the standard, like ddr 4 being double speed from 3

You don't just double the silicon on a package - it has non linear scaling for things like voltage (and IO, which is why rome's IO die is on 14nm) let alone the ability to actually build the thing defect free.

Bike vs truck.

Well isn't it explained by going to 7nm from 14?

This kills the kikes from Intlel

I get it anyway

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My first ibm pc had 64mb of ram.

Intel went from 45nm to 14nm++++, that's over 10 years and over 8x the area reduction without changing cache sizes, we have 32/256/2048kb now like we had in 2007

It's a big deal.

>first computer had 256 megs of ram
tfw first computer had 1k of ram

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Registers > L1 > L2 > L3 for access latency. Giving each core direct access to L3 would be a routing and timing closure nightmare so they break up physical routes with small local caches. You need to physically route around large caches and this leads to performance hits (lower clock) , so that's why people don't usually make a single massive l1 cache.

That would indicate AMD is changing it just because/marketing instead of it being a true selling point
>we're being different!

This should be great, running Linux with the CPU alone, also blazing fast RAM speed.

No, that would indicate Intel is fucking cheap and AMD is taking memory latency very seriously.
Also Intel is finally changing its caches with Icelake, in 2020

Bow down

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So fucking what. It's called progress. NASA landed on the Moon with a fucking toaster. Today we have a gazillion times more power, but we use it for gayming and mining memecoins. That's called regress.

550 dollars for a 1950 kek

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bow down to what? I get full cache as the 7s and who cares about memerippers

That depends entirely on how close to the CCX it is. Infinity fabric will need to be filled constantly.

>That ring

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it actually looks like a Rome era fortification, how based is AMD?

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The further you get away from the CPU (in a general sense) the longer your look-up times are for data. A complete cache miss (missing in the L1, L2, and L3) will result in you needing to look up data on RAM and be roughly ~1000 times slower than just grabbing it from your pipeline. Bigger cache means less misses, means less seeks, means smoother experience in basically everything you do.

Because the larger the die gets, the lower the yield gets during the manufacturing process. We're essentially limited by the laws of statistics when it comes to making larger dies, as a certain percentage of chips will have flaws that are outside of the acceptable tolerance for usability. Realistically, companies could try and perfect the manufacturing process to the point that they approached a 100% yield, but that would drive the manufacturing price up exponentially. Usually it's a lot more cost effective to accept a smaller yield and write-off a certain percentage of product rather than trying to make any process 100% perfect. Companies that produce microprocessors try to design CPUs with this in mind, and carefully balance performance improvements with manufacturing yield to maximize profit.

>It has 256MB of cache. It is presumed this lowers the latency.
It should actually be presumed this increases the latency. In what fucking world does increasing cache size lower latency?

>whats the point of having so much cache?

Mitigating memory bandwidth bottlenecking brought on by MOAR COARS on only 8 DDR4 channels.

Excuse me?

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delid dis

by parallelizing the access to the cache?

Request denied.

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>first computer
Blocks your path

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>tfw corelet

>5x13 grid
>that one open spot
thanks, you just gave me OCD

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IT'S OVER

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NONONONOAAAAARRRRGGGGHHH

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Apply yourself.

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More based than ever before.

I have waited my whole life for this type of sentiment.

>muh cores
>muh cache
>pls someone buy

WTF? amd is finished and bankrupt now!

It should be.

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kikeripper

>Why won't they make something like this but for pcs

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>gayman marketshare
lul.

Yes, that's the market that they've been targeting with poozen.

would programs be faster if caches were starting from 1mb? chips would be bigger I imagine

>256MB of total L3 cache?
More like 16*16MB, but yeah.
It's a Xeon killer by the virtue of going against 28c slightly better Skylake.

You need to take a break user. Maybe stretch or something